Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 8/08/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Resampler Intel® FPGA IP 11. Clipper Intel® FPGA IP 12. Clocked Video Input Intel® FPGA IP 13. Clocked Video to Full-Raster Converter Intel® FPGA IP 14. Clocked Video Output Intel® FPGA IP 15. Color Space Converter Intel® FPGA IP 16. Deinterlacer Intel® FPGA IP 17. FIR Filter Intel® FPGA IP 18. Frame Cleaner Intel® FPGA IP 19. Full-Raster to Clocked Video Converter Intel® FPGA IP 20. Full-Raster to Streaming Converter Intel® FPGA IP 21. Generic Crosspoint Intel® FPGA IP 22. Genlock Signal Router Intel® FPGA IP 23. Guard Bands Intel® FPGA IP 24. Mixer Intel® FPGA IP 25. Pixels in Parallel Converter Intel® FPGA IP 26. Scaler Intel® FPGA IP 27. Tone Mapping Operator Intel® FPGA IP 28. Test Pattern Generator Intel® FPGA IP 29. Video Frame Buffer Intel® FPGA IP 30. Video Streaming FIFO Intel® FPGA IP 31. Video Timing Generator Intel® FPGA IP 32. Warp Intel® FPGA IP 33. Design Security 34. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Resampler Intel® FPGA IP x
10.1. About the Chroma Resampler IP 10.2. Chroma Resampler IP Parameters 10.3. Chroma Resampler IP Functional Description 10.4. Chroma Resampler IP Registers 10.5. Chroma Resampler IP Software API
10.1. About the Chroma Resampler IP x
10.1.1. Chroma Resampler Performance and Resources
10.3. Chroma Resampler IP Functional Description x
10.3.1. Chroma Resampler IP Interfaces
11. Clipper Intel® FPGA IP x
11.1. About the Clipper IP 11.2. Clipper IP Parameters 11.3. Clipper IP Interfaces 11.4. Clipper IP Registers 11.5. Clipper IP Software API
11.1. About the Clipper IP x
11.1.1. Clipper IP Performance and Resources
12. Clocked Video Input Intel® FPGA IP x
12.1. About the Clocked Video Input IP 12.2. Initializing the Clocked Video Input IP 12.3. Clocked Video Input IP Parameters 12.4. Clocked Video Input IP Interfaces 12.5. Clocked Video Input IP Registers 12.6. Clocked Video Input IP Software API
12.1. About the Clocked Video Input IP x
12.1.1. Clocked Video Input IP Features 12.1.2. Clocked Video Input IP Performance and Resources
13. Clocked Video to Full-Raster Converter Intel® FPGA IP x
13.1. About the Clocked Video to Full-Raster Converter IP 13.2. Clocked Video to Full-Raster Converter Parameters 13.3. Clocked Video to Full-Raster Converter Block Description 13.4. Clocked Video Converter to Full-Raster IP Registers
13.1. About the Clocked Video to Full-Raster Converter IP x
13.1.1. Clocked Video to Full-Raster Converter Features 13.1.2. Clocked Video to Full-Raster Converter Performance and Resources
13.3. Clocked Video to Full-Raster Converter Block Description x
13.3.1. Clocked Video to Full-Raster Converter Interfaces
14. Clocked Video Output Intel® FPGA IP x
14.1. About the Clocked Video Output IP 14.2. Clocked Video Output IP Parameters 14.3. Clocked Video Output IP Functional Description 14.4. Clocked Video Output IP Interfaces 14.5. Clocked Video Output IP Registers 14.6. Clocked Video Output IP Software API
14.1. About the Clocked Video Output IP x
14.1.1. Clocked Video Output IP Performance and Resources 14.1.2. Clocked Video Output IP Features
15. Color Space Converter Intel® FPGA IP x
15.1. About the Color Space Converter IP 15.2. Color Space Converter IP Parameters 15.3. Color Space Converter IP Functional Description 15.4. Color Space Converter IP Registers 15.5. Color Space Converter IP Software API
15.1. About the Color Space Converter IP x
15.1.1. Color Space Converter IP Features 15.1.2. Color Space Converter IP Performance and Resources
15.3. Color Space Converter IP Functional Description x
15.3.1. Color Space Converter IP Interfaces
16. Deinterlacer Intel® FPGA IP x
16.1. About the Deinterlacer IP 16.2. Deinterlacer Parameters 16.3. Deinterlacer Interfaces 16.4. Deinterlacer Registers 16.5. Deinterlacer IP Software API
16.1. About the Deinterlacer IP x
16.1.1. Deinterlacer Performance and Resources
17. FIR Filter Intel® FPGA IP x
17.1. About the FIR Filter 17.2. FIR Filter Parameters 17.3. FIR Filter IP Operation 17.4. FIR Filter Interfaces 17.5. FIR Filter Registers 17.6. FIR Filter IP Software API
17.3. FIR Filter IP Operation x
17.3.1. FIR Filter Processing 17.3.2. FIR Filter Precision 17.3.3. FIR Coefficient Specification 17.3.4. FIR Filter Symmetry 17.3.5. Result to Output Data Type Conversion
17.3.4. FIR Filter Symmetry x
17.3.4.1. No Symmetry 17.3.4.2. Horizontal Symmetry 17.3.4.3. Vertical Symmetry 17.3.4.4. Horizontal and Vertical Symmetry 17.3.4.5. Diagonal Symmetry
18. Frame Cleaner Intel® FPGA IP x
18.1. About the Frame Cleaner IP 18.2. Frame Cleaner IP Parameters 18.3. Frame Cleaner IP Functional Description 18.4. Frame Cleaner IP Interfaces 18.5. Frame Cleaner IP Registers 18.6. Frame Cleaner IP Software API
18.1. About the Frame Cleaner IP x
18.1.1. Frame Cleaner IP Performance and Resources
19. Full-Raster to Clocked Video Converter Intel® FPGA IP x
19.1. About the Full-Raster to Clocked Video Converter 19.2. Full Raster to Clocked Video Converter Parameters 19.3. Full-Raster to Clocked Video Converter Block Description 19.4. Full-Raster to Clocked Video Converter Registers
19.1. About the Full-Raster to Clocked Video Converter x
19.1.1. Full-Raster to Clocked Video Converter Features 19.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
19.3. Full-Raster to Clocked Video Converter Block Description x
19.3.1. Full Raster to Clocked Video Converter Interfaces
20. Full-Raster to Streaming Converter Intel® FPGA IP x
20.1. About the Full-Raster to Streaming Converter IP 20.2. Full-Raster to Streaming Converter Parameters 20.3. Full-Raster to Streaming Converter Block Description
20.1. About the Full-Raster to Streaming Converter IP x
20.1.1. Full-Raster to Streaming Converter Features 20.1.2. Full-Raster to Streaming Converter Performance and Resources
20.3. Full-Raster to Streaming Converter Block Description x
20.3.1. Full-Raster to Streaming Converter Interfaces
21. Generic Crosspoint Intel® FPGA IP x
21.1. About the Generic Crosspoint IP 21.2. Generic Crosspoint IP Parameters 21.3. Generic Crosspoint IP Interfaces 21.4. Generic Crosspoint IP Registers 21.5. Generic Crosspoint IP Software API
21.1. About the Generic Crosspoint IP x
21.1.1. Generic Crosspoint IP Features 21.1.2. Generic Crosspoint Performance and Resources
22. Genlock Signal Router Intel® FPGA IP x
22.1. About the Genlock Signal Router IP 22.2. Genlock Signal Router IP Parameters 22.3. Genlock Signal Router IP Interfaces 22.4. Genlock Signal Router IP Registers 22.5. Genlock Signal Router IP Software API
22.1. About the Genlock Signal Router IP x
22.1.1. Genlock Signal Router IP Features 22.1.2. Genlock Signal Router IP Performance and Resources
23. Guard Bands Intel® FPGA IP x
23.1. About the Guard Bands IP 23.2. Guard Bands IP Parameters 23.3. Guard Bands IP Interfaces 23.4. Guard Bands IP Registers 23.5. Guard Bands IP Software API
23.1. About the Guard Bands IP x
23.1.1. Guard Bands IP Performance and Resources
24. Mixer Intel® FPGA IP x
24.1. About the Mixer IP 24.2. Mixer IP Parameters 24.3. Mixer IP Functional Description 24.4. Mixer IP Registers 24.5. Mixer IP Software API
24.1. About the Mixer IP x
24.1.1. Mixer IP Performance and Resources
24.3. Mixer IP Functional Description x
24.3.1. Mixer IP Interfaces
25. Pixels in Parallel Converter Intel® FPGA IP x
25.1. About the Pixels in Parallel Converter IP 25.2. Pixels in Parallel IP Converter Parameters 25.3. Pixels in Parallel Converter Interfaces 25.4. Pixels in Parallel Converter Registers 25.5. Pixels in Parallel Converter IP Software API
25.1. About the Pixels in Parallel Converter IP x
25.1.1. Pixels in Parallel IP Converter Performance and Resources
26. Scaler Intel® FPGA IP x
26.1. About the Scaler 26.2. Scaler IP Parameters 26.3. Scaler IP Functional Description 26.4. Scaler IP Registers 26.5. Scaler IP Software API
26.1. About the Scaler x
26.1.1. Scaler IP Performance and Resources
26.2. Scaler IP Parameters x
26.2.1. Updating Scaler IP Runtime Coefficients 26.2.2. Scaler Maximum Resolution
26.3. Scaler IP Functional Description x
26.3.1. Partial Frame Scaling 26.3.2. Scaler IP Interfaces
27. Tone Mapping Operator Intel® FPGA IP x
27.1. About the Tone Mapping Operator IP 27.2. TMO IP Parameters 27.3. TMO IP Block Description 27.4. TMO IP Registers 27.5. TMO IP Software API
27.1. About the Tone Mapping Operator IP x
27.1.1. TMO IP Features 27.1.2. TMO IP Performance and Resource Utilization
27.3. TMO IP Block Description x
27.3.1. TMO IP Interfaces 27.3.2. TMO IP Latency
28. Test Pattern Generator Intel® FPGA IP x
28.1. About the Test Pattern Generator IP 28.2. Test Pattern Generator IP Parameters 28.3. Test Pattern Generator IP Functional Description 28.4. Test Pattern Generator IP Registers 28.5. Test Pattern Generator IP Software API
28.1. About the Test Pattern Generator IP x
28.1.1. Test Pattern Generator IP Performance and Resources
28.3. Test Pattern Generator IP Functional Description x
28.3.1. Test Pattern Generator IP Interfaces
29. Video Frame Buffer Intel® FPGA IP x
29.1. About the Video Frame Buffer IP 29.2. Video Frame Buffer IP Parameters 29.3. Video Frame Buffer IP Functional Description 29.4. Video Frame Buffer IP Registers 29.5. Video Frame Buffer IP Software API
29.1. About the Video Frame Buffer IP x
29.1.1. Video Frame Buffer Performance and Resources
29.3. Video Frame Buffer IP Functional Description x
29.3.1. Video Frame Buffer IP Interfaces
30. Video Streaming FIFO Intel® FPGA IP x
30.1. About the Video Streaming FIFO IP 30.2. Video Streaming FIFO IP Parameters 30.3. Video Streaming FIFO IP Interfaces
30.1. About the Video Streaming FIFO IP x
30.1.1. Video Streaming FIFO IP Performance and Resources
31. Video Timing Generator Intel® FPGA IP x
31.1. About the Video Timing Generator IP 31.2. Video Timing Generator IP Parameters 31.3. Video Timing Generator IP Functional Description 31.4. Video Timing Generator IP Interfaces 31.5. Video Timing Generator IP Registers 31.6. Video Timing Generator IP Software API
31.1. About the Video Timing Generator IP x
31.1.1. Video Timing Generator IP Features 31.1.2. Video Timing Generator IP Performance and Resources
32. Warp Intel® FPGA IP x
32.1. About the Warp IP 32.2. Warp IP Parameters 32.3. Warp IP Block Description 32.4. Warp IP Registers 32.5. Warp IP Software API
32.1. About the Warp IP x
32.1.1. Warp IP Features 32.1.2. Warp IP Performance and Resource Utilization
32.3. Warp IP Block Description x
32.3.1. Warp IP Interfaces 32.3.2. Warp IP Latency 32.3.3. External Memory for Warp IP
32.5. Warp IP Software API x
32.5.1. Using Warp IP Software 32.5.2. Warp IP Software Code Examples
33. Design Security x
33.1. Memory Subsystems 33.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Resampler Intel® FPGA IP
11. Clipper Intel® FPGA IP
12. Clocked Video Input Intel® FPGA IP
13. Clocked Video to Full-Raster Converter Intel® FPGA IP
14. Clocked Video Output Intel® FPGA IP
15. Color Space Converter Intel® FPGA IP
16. Deinterlacer Intel® FPGA IP
17. FIR Filter Intel® FPGA IP
18. Frame Cleaner Intel® FPGA IP
19. Full-Raster to Clocked Video Converter Intel® FPGA IP
20. Full-Raster to Streaming Converter Intel® FPGA IP
21. Generic Crosspoint Intel® FPGA IP
22. Genlock Signal Router Intel® FPGA IP
23. Guard Bands Intel® FPGA IP
24. Mixer Intel® FPGA IP
25. Pixels in Parallel Converter Intel® FPGA IP
26. Scaler Intel® FPGA IP
27. Tone Mapping Operator Intel® FPGA IP
28. Test Pattern Generator Intel® FPGA IP
29. Video Frame Buffer Intel® FPGA IP
30. Video Streaming FIFO Intel® FPGA IP
31. Video Timing Generator Intel® FPGA IP
32. Warp Intel® FPGA IP
33. Design Security
34. Document Revision History for Video and Vision Processing Suite User Guide

28.5. Test Pattern Generator IP Software API

The IP includes software for run-time control. The IP does not fit any of the generic device models provided by the Nios II HAL and it exposes a set of dedicated accessors to the control and status registers. The IP driver structure inherits the base driver structure so all common methods defined in Video and Vision Processing IPs Software API are applicable.

Register definition header file: intel_vvp_tpg_regs.h

Include file: intel_vvp_tpg.h

Table 479.  Test Pattern Generator IP Software API
Name Description
intel_vvp_tpg_init Initialize the TPG instance
Intel_vvp_core_* .Accessors defined in Video and Vision Processing IPs Software Programming Model . Writable when Lite is on. Readable when Lite is off and Debug features is on.
intel_vvp_tpg_get_lite_mode Returns if Lite mode is on
intel_vvp_tpg_get_debug_enabled Returns if Lite mode is on
intel_vvp_tpg_get_num_patterns Returns the number of patterns available
intel_vvp_tpg_ctrl_in_enabled Returns if the control input is enabled
intel_vvp_tpg_get_bits_per_sample Returns the number of bits in a color sample
intel_vvp_tpg_get_pixels_in_parallel Returns the number of pixels processed in parallel per clock cycle
intel_vvp_tpg_get_pattern_data Returns pattern type and subsampling
intel_vvp_tpg_is_running Returns if the IP is producing data
intel_vvp_tpg_get_commit_status Returns if there are uncommitted writes
intel_vvp_tpg_get_status Reads the status register
intel_vvp_tpg_enable Starts/stops the IP
intel_vvp_tpg_start Start the IP
intel_vvp_tpg_stop Stops the IP
intel_vvp_tpg_is_enabled Returns if the IP is currently enabled
intel_vvp_tpg_set_pattern Select the current output pattern
intel_vvp_tpg_get_pattern Query the current output pattern
intel_vvp_tpg_get_fields_since_sequence_reset Returns the number of output fields generated since the sequence started
intel_vvp_tpg_set_pre_field_ctrl_pkts Number of packets from the control input to insert before each frame
intel_vvp_tpg_get_pre_field_ctrl_pkts Returns the number of control packets to insert before each frame
intel_vvp_tpg_set_post_field_ctrl_pkts Number of packets from the control input to insert after each frame
intel_vvp_tpg_get_post_field_ctrl_pkts Returns the number of control packets to insert after each frame
intel_vvp_tpg_set_bars_type Selects a type of color bars for the bar pattern
intel_vvp_tpg_get_bars_type Returns the current type of color bars
intel_vvp_tpg_set_colors Selects the color for the uniform pattern
intel_vvp_tpg_get_colors Returns the current uniform color
intel_vvp_tpg_commit_writes Commit all outstanding writes

enum eIntelVvpTpgPatternType

Members

kIntelVvpTpgBarsPattern – Bar pattern

kIntelVvpTpgUniformPattern – Uniform pattern

kIntelVvpTpgPathologicalPattern – Pattern that stresses SDI receiving equipment

kIntelVvpTpgInvalidPattern – Invalid pattern (used to indicate errors)

Description

Enumeration for the supported pattern types

enum eIntelVvpTpgPatternColor

Members

kIntelVvpTpgRgb – RGB 4:4:4

kIntelVvpTpgYcc444 – YCbCr/YUV 4:4:4

kIntelVvpTpgYcc422 – YCbCr/YUV 4:2:2

kIntelVvpTpgYcc420 – YCbCr/YUV 4:2:0

kIntelVvpTpgMono – Monochrome

kIntelVvpTpgInvalidColor – Invalid colorspace/subsampling (used to indicate errors)

Description

Enumeration for the supported color spaces and subsampling

enum eIntelVvpTpgBarsType

Members

kIntelVvpTpgColorBars – Standard color bars

kIntelVvpTpgGreyBars – Grey bars

kIntelVvpTpgBlackWhiteBars– Alternating black and white bars

kIntelVvpTpgInvalidBars – Invalid bar pattern (used to indicate errors)

Description

Enumeration for the supported color bar patterns

struct intel_vvp_tpg_pattern

Members

eIntelVvpTpgPatternType type – the configured type for the pattern

eIntelVvpTpgPatternColor color – The configured color space for the pattern

Description

Structure used to return the compile-time configuration for a given test pattern

intel_vvp_tpg_init

Prototype 
 int intel_vvp_tpg_init(intel_vvp_tpg_instance *instance, intel_vvp_core_base base);
Description

Initializes a TPG instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match or if the register map version is not supported. Otherwise, the function proceeds to read and store the IP compile-time parameterization. The instance does not fully initialized and should not be used further by the application if returning a non-zero error code.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

base – base address of the register map

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID (0x6AF7).

kIntelVvpCorePidErr if the product_id does not match with the TPG product ID

kIntelVvpCoreInstanceErr if the instance is a null pointer

kIntelVvpTpgRegMapVersionErr if the register map is not supported

intel_vvp_tpg_get_lite_mode

Prototype 
 bool intel_vvp_tpg_get_lite_mode(intel_vvp_tpg_instance *instance);
Description

Returns the value of the LITE_MODE register. The instance must be a valid intel_vvp_tpg_instance fully initialized

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

true if the IP is parameterized in lite mode

intel_vvp_tpg_get_debug_enabled

Prototype 
 int intel_vvp_tpg_get_debug_enabled(intel_vvp_tpg_instance *instance);
Description

Returns the value of the DEBUG_ENABLED register. The instance must be a valid intel_vvp_tpg_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

true if the IP is parameterized with debug features enabled

intel_vvp_tpg_get_num_patterns

Prototype 
 uint8_t intel_vvp_tpg_get_num_patterns(intel_vvp_tpg_instance* instance);
Description

Returns the value of the NUM_PATTERNS register. The instance must be a valid intel_vvp_tpg_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

The number of patterns available

intel_vvp_tpg_ctrl_in_enabled

Prototype

bool intel_vvp_tpg_ctrl_in_enabled(intel_vvp_tpg_instance* instance);

Description

Returns the value of the CTRL_IN_ENABLED register. The instance must be a valid intel_vvp_tpg_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

true if the IP is configured with a control input to insert control packets before and after each output fields

intel_vvp_tpg_get_bits_per_sample

Prototype 
 uint8_t intel_vvp_tpg_get_bits_per_sample(intel_vvp_tpg_instance* instance);
Description

Returns the value of the BPS register. The instance must be a valid intel_vvp_tpg_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

The compile-time bps parameter

intel_vvp_tpg_get_pixels_in_parallel

Prototype 
 uint8_t intel_vvp_tpg_get_pixels_in_parallel(intel_vvp_tpg_instance* instance);
Description

Returns the value of the PIP register. The instance must be a valid intel_vvp_tpg_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

The compile-time pixels in parallel parameter. This is the number of pixels generated per clock cycle.

intel_vvp_tpg_get_pattern_data

Prototype 
 int intel_vvp_tpg_get_pattern_data(intel_vvp_tpg_instance* instance, uint8_t pattern, intel_vvp_tpg_pattern* pattern_data);
Description

Returns the pattern configuration for a given pattern. The instance must be a valid intel_vvp_tpg_instance fully initialized. The selected pattern must be valid and pattern_data must point to a valid memory location to store the result.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

pattern – a valid pattern in the range [0..intel_vvp_get_num_patterns(instance)-1]

pattern_data – valid memory location for a intel_vvp_tpg_pattern structure

Returns

kIntelVvpCoreOk (0) in case of succes, a negative error code in case of error

kIntelVvpCoreInstanceErr if the instance is null

kIntelVvpTpgPatternNumErr if the pattern is out-of-range

kIntelVvpCoreNullPtrErr if pattern_data is null

Upon successful return, pattern_data is filled with the configuration for the selected pattern. This includes the pattern type (eIntelVvpTpgPatternType) and the colorspace/subsampling (eIntelVvpTpgPatternColor)

intel_vvp_tpg_is_running

Prototype 
 bool intel_vvp_tpg_is_running(intel_vvp_tpg_instance* instance);
Description

Reads and returns the running bit of the STATUS register. The instance must be a valid intel_vvp_tpg_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

True is the TPG is currently generating an output field, false when disabled and/or between two fields

intel_vvp_tpg_get_commit_status

Prototype 
 bool intel_vvp_tpg_get_commit_status(intel_vvp_tpg_instance* instance);
Description

Reads and returns the commit pending bit of the STATUS register. The instance must be a valid intel_vvp_tpg_instance fully initialized and configured in full mode.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

True is the TPG is configured in full mode and if the agent interface contains uncommitted writes.

intel_vvp_tpg_get_status

Prototype 
 uint8_t intel_vvp_tpg_get_status(intel_vvp_tpg_instance* instance);
Description

Reads and returns the STATUS register. The instance must be a valid intel_vvp_tpg_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

The value read from the status register

intel_vvp_tpg_enable

Prototype

int intel_vvp_tpg_enable(intel_vvp_tpg_instance* instance, bool enable);

Description

Starts the TPG IP. The instance must be a valid intel_vvp_tpg_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

enable – true to start the IP and generate fields, false to stop/pause the IP after the current field

Returns

kIntelVvpCoreOk (0) in case of success, otherwise negative error code. kIntelVvpCoreInstanceErr if the instance is null

intel_vvp_tpg_start

Prototype 
int intel_vvp_tpg_start(intel_vvp_tpg_instance* instance);
Description

Starts the TPG IP. The instance must be a valid intel_vvp_tpg_instance fully initialized. An alias for intel_vvp_tpg_enable(instance, true)

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

kIntelVvpCoreOk (0) in case of success, negative error code otherwise. kIntelVvpCoreInstanceErr if the instance is null

intel_vvp_tpg_stop

Prototype 
int intel_vvp_tpg_stop(intel_vvp_tpg_instance* instance);
Description

Stops the TPG IP. The instance must be a valid intel_vvp_tpg_instance fully initialized. An alias for intel_vvp_tpg_enable(instance, false)

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

kIntelVvpCoreOk (0) in case of success, negative error code otherwise. kIntelVvpCoreInstanceErr if the instance is null

intel_vvp_tpg_is_enabled

Prototype 
 bool intel_vvp_tpg_is_enabled(intel_vvp_tpg_instance* instance);
Description

Returns if the TPG IP is started or paused. The instance must be a valid intel_vvp_tpg_instance fully initialized. The state cannot be checked if debug is not enabled

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

true is the IP is enabled and in debug mode, false otherwise

intel_vvp_tpg_set_pattern

Prototype 
 int intel_vvp_tpg_set_pattern(intel_vvp_tpg_instance* instance, uint8_t pattern);
Description

Select/change the output test pattern. intel_vvp_tpg_instance must be valid and fully initialized. The pattern must be valid.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

pattern – A valid pattern configured at compile-time in the range [0..intel_vvp_get_num_patterns(instance)-1]

Returns

kIntelVvpCoreOk (0) in case of success, negative error code otherwise. kIntelVvpCoreInstanceErr if the instance is null

kIntelVvpTpgPatternNumErr if the pattern is out of range

intel_vvp_tpg_get_pattern

Prototype 
 uint8_t intel_vvp_tpg_get_pattern(intel_vvp_tpg_instance* instance);
Description

Returns the selected test pattern. The instance must be a valid intel_vvp_tpg_instance fully initialized. The pattern cannot be retrieved if debug is not enabled

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

Currently selected pattern or error code 255 if the instance is invalid or debug disabled

intel_vvp_tpg_get_fields_since_sequence_reset

Prototype 
 uint32_t intel_vvp_tpg_get_fields_since_sequence_reset(intel_vvp_tpg_instance* instance)
Description

Read and returns the FIELD_COUNT register. The field counter is automatically reset when the pattern changes or the image specifications change (after a write to the image info area). The value may remain undefined after a reset until the first field of the new sequence is sent.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

the field counter value

intel_vvp_tpg_set_pre_field_ctrl_pkts

Prototype 
 int intel_vvp_tpg_set_pre_field_ctrl_pkts(intel_vvp_tpg_instance* instance, uint32_t pkt_count);
Description

Sets the number of control packets to read and propagate from the ctrl_in input interface before each output field is generated and sent. The instance must be a valid intel_vvp_tpg_instance fully initialized, configured in full mode and the input control interface enabled

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

pkt_count – Number of control packets to propagate before each output field

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise

intel_vvp_tpg_get_pre_field_ctrl_pkts

Prototype 
 uint32_t intel_vvp_tpg_get_pre_field_ctrl_pkts(intel_vvp_tpg_instance* instance);
Description

Reads and returns the number of control packets to read and propagate from the ctrl_in input interface before each output field is generated and sent. The instance must be a valid intel_vvp_tpg_instance fully initialized, configured in full mode with debug enabled and the input control interface enabled

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

Number of control packets to propagate before each output field, 0 is returned if the instance does not support the feature or if debug is disabled

intel_vvp_tpg_set_post_field_ctrl_pkts

Prototype 
 int intel_vvp_tpg_set_post_field_ctrl_pkts(intel_vvp_tpg_instance* instance, uint32_t pkt_count);
Description

Sets the number of control packets to read and propagate from the ctrl_in input interface after each output field is generated and sent. The instance must be a valid intel_vvp_tpg_instance fully initialized, configured in full mode and the input control interface enabled

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

pkt_count – Number of control packets to propagate after each output field

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise.

intel_vvp_tpg_get_post_field_ctrl_pkts

Prototype 
 uint32_t intel_vvp_tpg_get_post_field_ctrl_pkts(intel_vvp_tpg_instance* instance);
Description

Reads and returns the number of control packets to read and propagate from the ctrl_in input interface after each output field is generated and sent. The instance must be a valid intel_vvp_tpg_instance fully initialized, configured in full mode with debug enabled and the input control interface enabled

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

Number of control packets to propagate after each output field, 0 is returned if the instance does not support the feature or if debug is disabled

intel_vvp_tpg_set_bars_type

Prototype 
 int intel_vvp_tpg_set_bars_type(intel_vvp_tpg_instance* instance, eIntelVvpTpgBarsType bar_type);
Description

Selects the type of color bars (black/white, grey, color) for patterns of type kIntelVvpTpgBarsPattern

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

bar_type – the type of color bars

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise.

intel_vvp_tpg_get_bars_type

Prototype

eIntelVvpTpgBarsType intel_vvp_tpg_set_bars_type(intel_vvp_tpg_instance* instance)

Description

Read and returns the selected bar type for patterns of type kIntelVvpTpgBarsPattern. Instance must be valid and debug enabled

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

the selected bar type, kIntelVvpTpgInvalidBars in case of error

intel_vvp_tpg_set_colors

Prototype 
 int intel_vvp_tpg_set_colors (intel_vvp_tpg_instance* instance, uint16_t color1, uint16_t color2, uint16_t color3);
Description

Selects the uniform color for patterns of type kIntelVvpTpgUniformPattern

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

color1, color2, color3 – the three new color sample values for the uniform pattern

The color samples must be in the range [0 .. (1 << intel_vvp_tpg_get_bits_per_sample(instance)) – 1]

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise.

kIntelVvpCoreInstanceErr if the instance is invalid

kIntelVvpTpgC1Err/ kIntelVvpTpgC2Err/ kIntelVvpTpgC3Err if the color sample is out-of-range

intel_vvp_tpg_get_colors

Prototype 
 int intel_vvp_tpg_get_colors(intel_vvp_tpg_instance* instance, uint16_t* color1, uint16_t* color2, uint16_t* color3)
Description

Reads and returns the selected color sample values for pattern of type kIntelVvpTpgUniformPattern. The instance must be a valid intel_vvp_tpg_instance with debug enabled. The three points that return values must point to valid memory locations containing uint16_t variables

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

color1, color2, color3 – three memory locations to store the returned color sample values

Returns

kIntelVvpCoreOk in case of success, negative error code otherwise.

kIntelVvpCoreInstanceErr, invalid instance (null pointer or debug disabled)

kIntelVvpCoreNullPtrErr, one of the uint16_t pointer is the null pointer

intel_vvp_tpg_commit_writes

Prototype 
 int intel_vvp_tpg_commit_writes(intel_vvp_tpg_instance* instance)
Description

Commits all pending writes before starting the next output field. The instance must be valid and parameterized in full mode.

Arguments

instance – pointer to the intel_vvp_tpg_instance software driver instance structure

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise.

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