Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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12.1. About the Clocked Video Input IP

The Clocked Video Input IP allows transferring video data between a timing-aware clocked video input interface and a timing-agnostic video streaming output interface. The IP provides a seamless conversion by removing video timing data from a full-raster bus and leaves just the pixel data in Intel FPGA streaming video format. Typically, the IP is a bridge to transfer data from video connectivity to video processing IP.
The IP accepts full-raster video input format as a full-raster interface of pixel data and timing markers embedded in the TDATA bus of an AXI4-S interface. Also, the IP filters out the timing markers from the TDATA bus and provides a video-active only data format on the output interfaces that conforms to the Intel FPGA streaming video protocol specification.
Figure 22. Clocked Video Input IP Block Diagram

The IP provides a wide variety of video statistic collection, e.g. frame counter, frame per seconds, active and blanking video frame information. All this information is accessible directly from a processor register interface.

Figure 23. Video Statistics Information

The figure provides an example of the video statistics information that the IP can provide for a 1080p60 video resolution.

By default, the IP only provides full-raster and video active high and width information as part of the video statistic collection. However, if you select the video telemetrics information in the GUI, the IP provides a more comprehensive set of video timing parameters. An optional frame per second counter provides you with an accurate frame rate estimation and its corresponding full-raster video clock.

Figure 24. Full-Raster TimingThe figure shows how the video statistics values collected by the IP correlates with a full-raster video frame.

The IP also provides an asynchronous FIFO buffer to handle the clock domain jump from input to output video domain. An optional frame cleaner is available at the back end of the IP. The frame cleaner allows you to automatically pad an incomplete frame (for example, because of an unplugged cable) by inserting a user configurable color pattern. You can turn on or off the frame cleaner at run time using the processor control interface.

Figure 25. Corrupted FrameThe figure shows an example where an output frame is corrupted, and the embedded frame cleaner adds padding (pink pixels) from the Clocked Video Input IP to complete the video output raster.