Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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12.3. Clocked Video Input IP Parameters

The IP offers compile-time parameters.
Table 103.  Clocked Video Input IP Parameters
Parameter Values Description
Video Format
Bits per color sample 8 to 16 Select the number of bits per color sample at the input
Number of pixels in parallel 1 to 8 Select the number of pixels transmitted every clock cycle.
Number of color planes 1 to 4 Select the number of color planes per pixel
General Settings
AXI4-S FR interface TREADY True or false Enable the TREADY signal as part of the full-raster interface
Output video line buffer depth 1024, 2048, 4096, 8192, 16384, 32768 Select the maximum depth of the output video line buffer
Output frame cleaner True or false Enable the output frame cleaner logic
Debug Information
Video telemetrics information True or false Enable the video telemetrics information logic
Frames per second counter True or false Enable the frames per second counter logic
Output clock frequency 1 to 1000000000 Select the output clock frequency in Hz
Figure 26. Clocked Video Input IP GUI