Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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14.3. Clocked Video Output IP Functional Description

The IP includes a merge block, which monitors the timing bus. It does not push back on the timing bus. The merge block stalls the video pixel data bus and test pattern generator pixel data bus when it sees the start of frame on the pixel data bus. The IP releases the pixel data buses when the timing bus contains the start of active pixel data.

Diagnostics report the status of the merge block via discreet output pins and the processor Interface.

Figure 34. External Timing Reference Bus
Figure 35. Embedded Video Timing Generator

The IP has a build-time option to include or exclude the tReady signal for the AXI4-S full-raster interface. The IP does not use this signal, but it allows you to connect to an AXI4-S full-raster bus that includes this signal. If the tReady signal is deasserted, the Clocked Video Output IP continues to output data.

The Clocked Video Output IP produces output on the transmit clock for the connectivity IP.

The processor interface operates on the processor clock domain. Intel recommends that you drive the processor Interface from a known stable clock, such as a dedicated processor clock. Do not drive with the transmit clock for the connectivity IP, which can be unstable. For example when standards change, the transmit clock can be unstable. If you use the transmit clock to clock the processor interface it can potentially corrupt the processor interface.