Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

17.3.1. FIR Filter Processing

The FIR II IP calculates the output pixel values in 3 stages.
  1. Creates kernel

    The IP creates an N×M array of input pixels around the input pixel at the same position in the input image as the position of the output pixel in the output image. This center pixel has (N-1)/2 pixels to its left and N/2 pixels to its right in the array, and (M-1)/2 lines above it and M/2 lines below it.

    When the pixels to the left, right, above, or below the center pixel in the kernel extend beyond the edges of the image, the filter uses either replication of the edge pixel or full data mirroring, according to the value of a compile time parameter.

  2. Convolutes

    The IP multiplies each pixel in the N×M input array by the corresponding coefficient in the N×M coefficient array. The IP sums the results to produce the filtered value.

    The FIR Filter II IP retains full precision throughout the calculation of each filtered value, with all rounding and saturation to the required output precision applied as a final stage.

  3. Rounds and saturates.

    The IP rounds and saturates the resulting full precision filtered value according to the output precision specification