Video and Vision Processing Suite Intel® FPGA IP User Guide

Download PDF
ID 683329
Date 8/08/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Resampler Intel® FPGA IP 11. Clipper Intel® FPGA IP 12. Clocked Video Input Intel® FPGA IP 13. Clocked Video to Full-Raster Converter Intel® FPGA IP 14. Clocked Video Output Intel® FPGA IP 15. Color Space Converter Intel® FPGA IP 16. Deinterlacer Intel® FPGA IP 17. FIR Filter Intel® FPGA IP 18. Frame Cleaner Intel® FPGA IP 19. Full-Raster to Clocked Video Converter Intel® FPGA IP 20. Full-Raster to Streaming Converter Intel® FPGA IP 21. Generic Crosspoint Intel® FPGA IP 22. Genlock Signal Router Intel® FPGA IP 23. Guard Bands Intel® FPGA IP 24. Mixer Intel® FPGA IP 25. Pixels in Parallel Converter Intel® FPGA IP 26. Scaler Intel® FPGA IP 27. Tone Mapping Operator Intel® FPGA IP 28. Test Pattern Generator Intel® FPGA IP 29. Video Frame Buffer Intel® FPGA IP 30. Video Streaming FIFO Intel® FPGA IP 31. Video Timing Generator Intel® FPGA IP 32. Warp Intel® FPGA IP 33. Design Security 34. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Resampler Intel® FPGA IP x
10.1. About the Chroma Resampler IP 10.2. Chroma Resampler IP Parameters 10.3. Chroma Resampler IP Functional Description 10.4. Chroma Resampler IP Registers 10.5. Chroma Resampler IP Software API
10.1. About the Chroma Resampler IP x
10.1.1. Chroma Resampler Performance and Resources
10.3. Chroma Resampler IP Functional Description x
10.3.1. Chroma Resampler IP Interfaces
11. Clipper Intel® FPGA IP x
11.1. About the Clipper IP 11.2. Clipper IP Parameters 11.3. Clipper IP Interfaces 11.4. Clipper IP Registers 11.5. Clipper IP Software API
11.1. About the Clipper IP x
11.1.1. Clipper IP Performance and Resources
12. Clocked Video Input Intel® FPGA IP x
12.1. About the Clocked Video Input IP 12.2. Initializing the Clocked Video Input IP 12.3. Clocked Video Input IP Parameters 12.4. Clocked Video Input IP Interfaces 12.5. Clocked Video Input IP Registers 12.6. Clocked Video Input IP Software API
12.1. About the Clocked Video Input IP x
12.1.1. Clocked Video Input IP Features 12.1.2. Clocked Video Input IP Performance and Resources
13. Clocked Video to Full-Raster Converter Intel® FPGA IP x
13.1. About the Clocked Video to Full-Raster Converter IP 13.2. Clocked Video to Full-Raster Converter Parameters 13.3. Clocked Video to Full-Raster Converter Block Description 13.4. Clocked Video Converter to Full-Raster IP Registers
13.1. About the Clocked Video to Full-Raster Converter IP x
13.1.1. Clocked Video to Full-Raster Converter Features 13.1.2. Clocked Video to Full-Raster Converter Performance and Resources
13.3. Clocked Video to Full-Raster Converter Block Description x
13.3.1. Clocked Video to Full-Raster Converter Interfaces
14. Clocked Video Output Intel® FPGA IP x
14.1. About the Clocked Video Output IP 14.2. Clocked Video Output IP Parameters 14.3. Clocked Video Output IP Functional Description 14.4. Clocked Video Output IP Interfaces 14.5. Clocked Video Output IP Registers 14.6. Clocked Video Output IP Software API
14.1. About the Clocked Video Output IP x
14.1.1. Clocked Video Output IP Performance and Resources 14.1.2. Clocked Video Output IP Features
15. Color Space Converter Intel® FPGA IP x
15.1. About the Color Space Converter IP 15.2. Color Space Converter IP Parameters 15.3. Color Space Converter IP Functional Description 15.4. Color Space Converter IP Registers 15.5. Color Space Converter IP Software API
15.1. About the Color Space Converter IP x
15.1.1. Color Space Converter IP Features 15.1.2. Color Space Converter IP Performance and Resources
15.3. Color Space Converter IP Functional Description x
15.3.1. Color Space Converter IP Interfaces
16. Deinterlacer Intel® FPGA IP x
16.1. About the Deinterlacer IP 16.2. Deinterlacer Parameters 16.3. Deinterlacer Interfaces 16.4. Deinterlacer Registers 16.5. Deinterlacer IP Software API
16.1. About the Deinterlacer IP x
16.1.1. Deinterlacer Performance and Resources
17. FIR Filter Intel® FPGA IP x
17.1. About the FIR Filter 17.2. FIR Filter Parameters 17.3. FIR Filter IP Operation 17.4. FIR Filter Interfaces 17.5. FIR Filter Registers 17.6. FIR Filter IP Software API
17.3. FIR Filter IP Operation x
17.3.1. FIR Filter Processing 17.3.2. FIR Filter Precision 17.3.3. FIR Coefficient Specification 17.3.4. FIR Filter Symmetry 17.3.5. Result to Output Data Type Conversion
17.3.4. FIR Filter Symmetry x
17.3.4.1. No Symmetry 17.3.4.2. Horizontal Symmetry 17.3.4.3. Vertical Symmetry 17.3.4.4. Horizontal and Vertical Symmetry 17.3.4.5. Diagonal Symmetry
18. Frame Cleaner Intel® FPGA IP x
18.1. About the Frame Cleaner IP 18.2. Frame Cleaner IP Parameters 18.3. Frame Cleaner IP Functional Description 18.4. Frame Cleaner IP Interfaces 18.5. Frame Cleaner IP Registers 18.6. Frame Cleaner IP Software API
18.1. About the Frame Cleaner IP x
18.1.1. Frame Cleaner IP Performance and Resources
19. Full-Raster to Clocked Video Converter Intel® FPGA IP x
19.1. About the Full-Raster to Clocked Video Converter 19.2. Full Raster to Clocked Video Converter Parameters 19.3. Full-Raster to Clocked Video Converter Block Description 19.4. Full-Raster to Clocked Video Converter Registers
19.1. About the Full-Raster to Clocked Video Converter x
19.1.1. Full-Raster to Clocked Video Converter Features 19.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
19.3. Full-Raster to Clocked Video Converter Block Description x
19.3.1. Full Raster to Clocked Video Converter Interfaces
20. Full-Raster to Streaming Converter Intel® FPGA IP x
20.1. About the Full-Raster to Streaming Converter IP 20.2. Full-Raster to Streaming Converter Parameters 20.3. Full-Raster to Streaming Converter Block Description
20.1. About the Full-Raster to Streaming Converter IP x
20.1.1. Full-Raster to Streaming Converter Features 20.1.2. Full-Raster to Streaming Converter Performance and Resources
20.3. Full-Raster to Streaming Converter Block Description x
20.3.1. Full-Raster to Streaming Converter Interfaces
21. Generic Crosspoint Intel® FPGA IP x
21.1. About the Generic Crosspoint IP 21.2. Generic Crosspoint IP Parameters 21.3. Generic Crosspoint IP Interfaces 21.4. Generic Crosspoint IP Registers 21.5. Generic Crosspoint IP Software API
21.1. About the Generic Crosspoint IP x
21.1.1. Generic Crosspoint IP Features 21.1.2. Generic Crosspoint Performance and Resources
22. Genlock Signal Router Intel® FPGA IP x
22.1. About the Genlock Signal Router IP 22.2. Genlock Signal Router IP Parameters 22.3. Genlock Signal Router IP Interfaces 22.4. Genlock Signal Router IP Registers 22.5. Genlock Signal Router IP Software API
22.1. About the Genlock Signal Router IP x
22.1.1. Genlock Signal Router IP Features 22.1.2. Genlock Signal Router IP Performance and Resources
23. Guard Bands Intel® FPGA IP x
23.1. About the Guard Bands IP 23.2. Guard Bands IP Parameters 23.3. Guard Bands IP Interfaces 23.4. Guard Bands IP Registers 23.5. Guard Bands IP Software API
23.1. About the Guard Bands IP x
23.1.1. Guard Bands IP Performance and Resources
24. Mixer Intel® FPGA IP x
24.1. About the Mixer IP 24.2. Mixer IP Parameters 24.3. Mixer IP Functional Description 24.4. Mixer IP Registers 24.5. Mixer IP Software API
24.1. About the Mixer IP x
24.1.1. Mixer IP Performance and Resources
24.3. Mixer IP Functional Description x
24.3.1. Mixer IP Interfaces
25. Pixels in Parallel Converter Intel® FPGA IP x
25.1. About the Pixels in Parallel Converter IP 25.2. Pixels in Parallel IP Converter Parameters 25.3. Pixels in Parallel Converter Interfaces 25.4. Pixels in Parallel Converter Registers 25.5. Pixels in Parallel Converter IP Software API
25.1. About the Pixels in Parallel Converter IP x
25.1.1. Pixels in Parallel IP Converter Performance and Resources
26. Scaler Intel® FPGA IP x
26.1. About the Scaler 26.2. Scaler IP Parameters 26.3. Scaler IP Functional Description 26.4. Scaler IP Registers 26.5. Scaler IP Software API
26.1. About the Scaler x
26.1.1. Scaler IP Performance and Resources
26.2. Scaler IP Parameters x
26.2.1. Updating Scaler IP Runtime Coefficients 26.2.2. Scaler Maximum Resolution
26.3. Scaler IP Functional Description x
26.3.1. Partial Frame Scaling 26.3.2. Scaler IP Interfaces
27. Tone Mapping Operator Intel® FPGA IP x
27.1. About the Tone Mapping Operator IP 27.2. TMO IP Parameters 27.3. TMO IP Block Description 27.4. TMO IP Registers 27.5. TMO IP Software API
27.1. About the Tone Mapping Operator IP x
27.1.1. TMO IP Features 27.1.2. TMO IP Performance and Resource Utilization
27.3. TMO IP Block Description x
27.3.1. TMO IP Interfaces 27.3.2. TMO IP Latency
28. Test Pattern Generator Intel® FPGA IP x
28.1. About the Test Pattern Generator IP 28.2. Test Pattern Generator IP Parameters 28.3. Test Pattern Generator IP Functional Description 28.4. Test Pattern Generator IP Registers 28.5. Test Pattern Generator IP Software API
28.1. About the Test Pattern Generator IP x
28.1.1. Test Pattern Generator IP Performance and Resources
28.3. Test Pattern Generator IP Functional Description x
28.3.1. Test Pattern Generator IP Interfaces
29. Video Frame Buffer Intel® FPGA IP x
29.1. About the Video Frame Buffer IP 29.2. Video Frame Buffer IP Parameters 29.3. Video Frame Buffer IP Functional Description 29.4. Video Frame Buffer IP Registers 29.5. Video Frame Buffer IP Software API
29.1. About the Video Frame Buffer IP x
29.1.1. Video Frame Buffer Performance and Resources
29.3. Video Frame Buffer IP Functional Description x
29.3.1. Video Frame Buffer IP Interfaces
30. Video Streaming FIFO Intel® FPGA IP x
30.1. About the Video Streaming FIFO IP 30.2. Video Streaming FIFO IP Parameters 30.3. Video Streaming FIFO IP Interfaces
30.1. About the Video Streaming FIFO IP x
30.1.1. Video Streaming FIFO IP Performance and Resources
31. Video Timing Generator Intel® FPGA IP x
31.1. About the Video Timing Generator IP 31.2. Video Timing Generator IP Parameters 31.3. Video Timing Generator IP Functional Description 31.4. Video Timing Generator IP Interfaces 31.5. Video Timing Generator IP Registers 31.6. Video Timing Generator IP Software API
31.1. About the Video Timing Generator IP x
31.1.1. Video Timing Generator IP Features 31.1.2. Video Timing Generator IP Performance and Resources
32. Warp Intel® FPGA IP x
32.1. About the Warp IP 32.2. Warp IP Parameters 32.3. Warp IP Block Description 32.4. Warp IP Registers 32.5. Warp IP Software API
32.1. About the Warp IP x
32.1.1. Warp IP Features 32.1.2. Warp IP Performance and Resource Utilization
32.3. Warp IP Block Description x
32.3.1. Warp IP Interfaces 32.3.2. Warp IP Latency 32.3.3. External Memory for Warp IP
32.5. Warp IP Software API x
32.5.1. Using Warp IP Software 32.5.2. Warp IP Software Code Examples
33. Design Security x
33.1. Memory Subsystems 33.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Resampler Intel® FPGA IP
11. Clipper Intel® FPGA IP
12. Clocked Video Input Intel® FPGA IP
13. Clocked Video to Full-Raster Converter Intel® FPGA IP
14. Clocked Video Output Intel® FPGA IP
15. Color Space Converter Intel® FPGA IP
16. Deinterlacer Intel® FPGA IP
17. FIR Filter Intel® FPGA IP
18. Frame Cleaner Intel® FPGA IP
19. Full-Raster to Clocked Video Converter Intel® FPGA IP
20. Full-Raster to Streaming Converter Intel® FPGA IP
21. Generic Crosspoint Intel® FPGA IP
22. Genlock Signal Router Intel® FPGA IP
23. Guard Bands Intel® FPGA IP
24. Mixer Intel® FPGA IP
25. Pixels in Parallel Converter Intel® FPGA IP
26. Scaler Intel® FPGA IP
27. Tone Mapping Operator Intel® FPGA IP
28. Test Pattern Generator Intel® FPGA IP
29. Video Frame Buffer Intel® FPGA IP
30. Video Streaming FIFO Intel® FPGA IP
31. Video Timing Generator Intel® FPGA IP
32. Warp Intel® FPGA IP
33. Design Security
34. Document Revision History for Video and Vision Processing Suite User Guide

12.5. Clocked Video Input IP Registers

The IP allows runtime configuration of parameters via Avalon memory-mapped processor register interface.
Table 105.  Clocked Video Input IP Registers
Offset Register Access Description
Parameterization registers
0x000 VID_PID RO Read this register to retrieve clocked video input product ID. This register always returns 0x6FA7_0170.
0x004 VERSION_NUMBER RO

Read this register to retrieve the version information for the Intel Quartus release that Intel uses to build this IP.

0x008-

0x014

RESERVED RO
0x018 NUMBER OF PIXELS IN PARALLEL RO Read this register to determine the number of pixels processed per clock cycle.
0x01C NUMBER OF COLOR PLANES RO Read this register to determine the number of color planes.
0x020 NUMBER OF BITS PER COLOR SAMPLE RO Read this register to determine the number of bits per color sample
0x024 AXI4-S FR INTERFACE TREADY RO Read this register to determine if the full-raster interface includes the TREADY conduit
0x028 OUTPUT VIDEO LINE BUFFER DEPTH RO Read this register to determine the depth of the output line buffer
0x02C VIDEO TELEMETRICS INFORMATION RO Read this register to determine if the optional logic to retrieve video timing information was included for this IP
0x030 OUTPUT CLOCK FREQUENCY RO Read this register to determine the output clock frequency
Core Specific Registers
0x148 Control RW Sets the IP control mode of operation
0x14C Status RW Returns the status of the IP
0x150 Interrupt_Alarm RW Interrupt status and clear bits
0x154 Horizontal_sample_count RO Returns the detected width count per line of the video streams.
0x158 Active_line_count RO Returns the detected height count per frame of the video streams excluding blanking.
0x15C Total_line_count RO Returns the detected height count per frame of the video streams including blanking.
0x160 Ref_lock_cfg1 RW The IP reference width and height values to assert the video locked signal
0x164 Ref_lock_cfg2 RW The IP reference number of frames and lines values to assert the video locked signal
0x168 Clk_in_freq_count RO Returns the detected frequency value of the input clock
0x16C Tpg_cfg1 RW Configure the value of the color plane 4 and color plane 3
0x170 Tpg_cfg2 RW Configure the value of the color plane 2 and color plane 1
0x174-0x184 Reserved -
0x188 Total_fr_pixel_count RO Returns the detected total number of pixels on the input full-raster frame including blanking
0x18C Total_active_pixel_count RO Return the detected total number of pixels on the input full-raster frame excluding blanking
0x190 Fr_pixel_line_count RO Returns the detected total number of pixels per line including and excluding blanking.
0x194 Hpulse_count RO Returns the Hsync width value if the video format uses Sync timing mode, otherwise it returns the total horizontal blanking period.
0x198 Hbp_hfp_count RO Returns the horizontal back porch width value if the video format uses Sync timing mode, otherwise it returns 0.
0x19C f0f1_vfp_count RO Returns the vertical front porch value for field 0 and field 1.
0x1A0 f0f1_vpulse_count_reg RO Returns the Vsync value for field 0 and field 1.
0x1A4 f0f1_vbp_count_reg RO Returns the vertical back porch value for field 0 and field 1.
0x1A8 Hpulse_ref RW Reference value for the expected Hsync parameter. 19
0x1AC Hbp_hfp_ref RW Reference value for the expected horizontal front and back porch parameters.19
0x1B0 f0f1_vfp_ref RW Reference value for the expected vertical front porch parameter. 19
0x1B4 f0f1_vpulse_ref RW Reference value for the expected Vsync parameter. 19
0x1B8 f0f1_vbp_ref RW Reference value for the expected vertical back porch parameter. 19

Register Bit Descriptions

Table 106.  Vid_pid
Bits Description
31:0 Product Identification Number

Table 107.  Version_number_pid
Bits Description
31:0 IP Version Number
Table 108.  NUMBER OF PIXELS IN PARALLEL
Bits Description
31:0 The number of pixels transmitted every clock cycle.
Table 109.  NUMBER OF COLOR PLANES
Bits Description
31:0 The number of color planes per sample at the input
Table 110.  NUMBER OF BITS PER COLOR SAMPLE
Bits Description
31:0 The number of bits per color sample
Table 111.  AXI4-S FR INTERFACE TREADY
Bits Description
31:0 Enable the TREADY signal as part of the full-raster interface
Table 112.  OUTPUT VIDEO LINE BUFFER DEPTH
Bits Description
31:0 The maximum depth of the output video line buffer
Table 113.  VIDEO TELEMETRICS INFORMATION
Bits Description
31:0 Enable the video telemetrics information logic
Table 114.  OUTPUT CLOCK FREQUENCY
Bits Description
31:0 The output clock frequency in Hz
Table 115.  Control
Bits Name Description
7 ext_locked_ena Setting this bit enables an external video locked signal to indicate when a stable video stream is present on the input.
6 hsync_pol If auto polarity detection is off, set this bit to override the polarity for the hsync/hpulse signal
5 vsync_pol If auto polarity detection is off, set this bit to override the polarity for the vsync/vpulse signal
4 auto_pol_dect Set this bit to turn on the video sync autopolarity detection.
3 mux_out_sel Set this bit to turn on the output frame cleaner.
2 irq2_ena Set this bit to turn on the end of frame video interrupt.
1 irq1_ena Set this bit to turn on the status update interrupt
0 Go bit Set this bit to 1 to start IP data output on the next video frame boundary.
Table 116.  Status
Bits Name Description
9 hsync_pol_detc This bit indicates the detected polarity for the horizontal signal
8 vsync_pol_detc This bit indicates the detected polarity for the vertical signal
7 drop_vid This bit indicates that a frame was not completed
6 - Reserved
5 external_vid_locked This bit indicates if the external video locked has been asserted
4 internal_vid_locked This bit indicates if the external video locked has been asserted
3 overflow_sticky This bit indicates if a FIFO overflow occurs. Writing 1 to this bit clears it
2 vid_sync_mode This bit indicates if the input video frame is using Blank timing or Sync timing
1 interlaced_detected This bit indicates if an interlaced format has been detected
0 Status This bit indicates if the input resolution has changed.
Table 117.  Interrupt_Alarms
Bits Name Description
14 hfp_alarm_sticky This bit indicates that the reference hfp counter is not matching the actual hfp counter. Set this bit to 1 to clear it.
13 hpulse_alarm_sticky This bit indicates that the reference hpulse counter is not matching the actual hpulse counter. Set this bit to 1 to clear it.
12 hbp_alarm_sticky . This bit indicates that the reference hbp counter is not matching the actual hbp counter. Set this bit to 1 to clear it.
11 f0_vfp_alarm_sticky This bit indicates that the reference vfp counter is not matching the actual vfp counter. Set this bit to 1 to clear it.
10 f0_vpulse_alarm_sticky This bit indicates that the reference vpulse counter is not matching the actual vpulse counter. Set this bit to 1 to clear it.
9 f0_vbp_alarm_sticky . This bit indicates that the reference vbp counter is not matching the actual vbp counter. Set this bit to 1 to clear it.
8 f1_vfp_alarm_sticky This bit indicates that the reference vfp counter is not matching the actual vfp counter. Setting this bit to 1 to clear it.
7 f1_vpulse_alarm_sticky This bit indicates that the reference vpulse counter is not matching the actual vpulse counter. Set this bit to 1 to clear it.
6 f1_vbp_alarm_sticky . This bit indicates that the reference vbp counter is not matching the actual vbp counter. Set this bit to 1 to clear it.
5 video_width_alarm_sticky This bit indicates that the reference width counter is not matching the actual width counter. Set this bit to 1 to clear it.
4 video_height_alarm_sticky This bit indicates that the reference height counter is not matching the actual height counter. Set this bit to 1 to clear it.
3 video_frames_alarm_sticky This bit indicates that the reference frame counter is not matching the actual frame counter. Set this bit to 1 to clear it.
2 video_lines_alarm_sticky This bit indicates that the reference line counter is not matching the actual line counter. Set this bit to 1 to clear it.
1 eof_sticky This bit indicates the end of frame. Set this bit to 1 to clear it.
0 irq_status_sticky This bit indicates a change of input video resolution. Set this bit to 1 to clear it.
Table 118.  Horizontal_sample_count
Bits Description
31:16 The total number of pixels per line
15:0 The active number of pixels per line
Table 119.  Active_line_count
Bits Description
31:16 The active number of lines for field 0
15:0 The active number of lines for field 1
Table 120.  Total_line_count
Bits Description
31:16 The total (blanking + active) number of lines for field 0
15:0 The total (blanking + active) number of lines for field 1
Table 121.  Ref_lock_cfg1
Bits Description
31:16 The expected output video height to assert video locked signal
15:0 The expected output video width to assert video locked signal
Table 122.  Ref_lock_cfg2
Bits Description
31:16 The number of consecutive valid frames before asserting video locked signal
15:0 The number of consecutive valid lines before asserting video locked signal
Table 123.  Clk_in_freq_count
Bits Description
31:0 The value of input clock frequency in Hz
Table 124.  Tpg_cfg1_reg
Bits Description
31:16 Pixel value for the color plane # 4
15:0 Pixel value for the color plane # 3
Table 125.  Tpg_cfg2
Bits Description
31:16 Pixel value for the color plane # 2
15:0 Pixel value for the color plane # 1
Table 126.  Total_fr_pixel_count
Bits Description
31:0 Total number of full-raster pixels per frame
Table 127.  Total_active_pixel_count
Bits Description
31:0 Total number of actives pixels per frame
Table 128.  Fr_pixel_line_count
Bits Description
31:16 Full-raster blanking pixels per line
15:0 Full-raster blanking lines per frame
Table 129.  Hpulse_count
Bits Description
15:0 Horizontal (H) counter
Table 130.  Hbp_hfp_count
Bits Description
31:16 Horizontal front porch counter
15:0 Horizontal back porch counter
Table 131.  F0f1_vfp_count
Bits Description
31:16 Vertical front porch counter for field 0
15:0 Vertical front porch counter for field 1
Table 132.  F0f1_vpulse_count
Bits Description
31:16 Vertical reference for field 0
15:0 Vertical counter for field 1
Table 133.  F0f1_vbp_count
Bits Description
31:16 Vertical back porch counter for field 0
15:0 Vertical back porch counter for field 1
Table 134.  Hpulse_ref
Bits Description
15:0 Horizontal (H) reference counter
Table 135.  Hbp_hfp_ref
Bits Description
31:16 Horizontal front porch reference counter
15:0 Horizontal back porch reference counter
Table 136.  F0f1_vfp_ref
Bits Description
31:16 Vertical front porch reference counter for field 0
15:0 Vertical front porch reference counter for field 1
Table 137.  F0f1_vpulse_ref
Bits Description
31:16 Vertical (V) reference counter for field 0
15:0 Vertical (V) reference counter for field 1
Table 138.  F0f1_vbp_ref
Bits Description
31:16 Vertical back porch reference counter for field 0
15:0 Vertical back porch reference counter for field 1
19 If the corresponding alarm is on, and the detected value do not match this register, the IP asserts a sticky bit to indicate a mismatch.
Level Two Title