Video and Vision Processing Suite Intel® FPGA IP User Guide

Download PDF
ID 683329
Date 8/08/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Resampler Intel® FPGA IP 11. Clipper Intel® FPGA IP 12. Clocked Video Input Intel® FPGA IP 13. Clocked Video to Full-Raster Converter Intel® FPGA IP 14. Clocked Video Output Intel® FPGA IP 15. Color Space Converter Intel® FPGA IP 16. Deinterlacer Intel® FPGA IP 17. FIR Filter Intel® FPGA IP 18. Frame Cleaner Intel® FPGA IP 19. Full-Raster to Clocked Video Converter Intel® FPGA IP 20. Full-Raster to Streaming Converter Intel® FPGA IP 21. Generic Crosspoint Intel® FPGA IP 22. Genlock Signal Router Intel® FPGA IP 23. Guard Bands Intel® FPGA IP 24. Mixer Intel® FPGA IP 25. Pixels in Parallel Converter Intel® FPGA IP 26. Scaler Intel® FPGA IP 27. Tone Mapping Operator Intel® FPGA IP 28. Test Pattern Generator Intel® FPGA IP 29. Video Frame Buffer Intel® FPGA IP 30. Video Streaming FIFO Intel® FPGA IP 31. Video Timing Generator Intel® FPGA IP 32. Warp Intel® FPGA IP 33. Design Security 34. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Resampler Intel® FPGA IP x
10.1. About the Chroma Resampler IP 10.2. Chroma Resampler IP Parameters 10.3. Chroma Resampler IP Functional Description 10.4. Chroma Resampler IP Registers 10.5. Chroma Resampler IP Software API
10.1. About the Chroma Resampler IP x
10.1.1. Chroma Resampler Performance and Resources
10.3. Chroma Resampler IP Functional Description x
10.3.1. Chroma Resampler IP Interfaces
11. Clipper Intel® FPGA IP x
11.1. About the Clipper IP 11.2. Clipper IP Parameters 11.3. Clipper IP Interfaces 11.4. Clipper IP Registers 11.5. Clipper IP Software API
11.1. About the Clipper IP x
11.1.1. Clipper IP Performance and Resources
12. Clocked Video Input Intel® FPGA IP x
12.1. About the Clocked Video Input IP 12.2. Initializing the Clocked Video Input IP 12.3. Clocked Video Input IP Parameters 12.4. Clocked Video Input IP Interfaces 12.5. Clocked Video Input IP Registers 12.6. Clocked Video Input IP Software API
12.1. About the Clocked Video Input IP x
12.1.1. Clocked Video Input IP Features 12.1.2. Clocked Video Input IP Performance and Resources
13. Clocked Video to Full-Raster Converter Intel® FPGA IP x
13.1. About the Clocked Video to Full-Raster Converter IP 13.2. Clocked Video to Full-Raster Converter Parameters 13.3. Clocked Video to Full-Raster Converter Block Description 13.4. Clocked Video Converter to Full-Raster IP Registers
13.1. About the Clocked Video to Full-Raster Converter IP x
13.1.1. Clocked Video to Full-Raster Converter Features 13.1.2. Clocked Video to Full-Raster Converter Performance and Resources
13.3. Clocked Video to Full-Raster Converter Block Description x
13.3.1. Clocked Video to Full-Raster Converter Interfaces
14. Clocked Video Output Intel® FPGA IP x
14.1. About the Clocked Video Output IP 14.2. Clocked Video Output IP Parameters 14.3. Clocked Video Output IP Functional Description 14.4. Clocked Video Output IP Interfaces 14.5. Clocked Video Output IP Registers 14.6. Clocked Video Output IP Software API
14.1. About the Clocked Video Output IP x
14.1.1. Clocked Video Output IP Performance and Resources 14.1.2. Clocked Video Output IP Features
15. Color Space Converter Intel® FPGA IP x
15.1. About the Color Space Converter IP 15.2. Color Space Converter IP Parameters 15.3. Color Space Converter IP Functional Description 15.4. Color Space Converter IP Registers 15.5. Color Space Converter IP Software API
15.1. About the Color Space Converter IP x
15.1.1. Color Space Converter IP Features 15.1.2. Color Space Converter IP Performance and Resources
15.3. Color Space Converter IP Functional Description x
15.3.1. Color Space Converter IP Interfaces
16. Deinterlacer Intel® FPGA IP x
16.1. About the Deinterlacer IP 16.2. Deinterlacer Parameters 16.3. Deinterlacer Interfaces 16.4. Deinterlacer Registers 16.5. Deinterlacer IP Software API
16.1. About the Deinterlacer IP x
16.1.1. Deinterlacer Performance and Resources
17. FIR Filter Intel® FPGA IP x
17.1. About the FIR Filter 17.2. FIR Filter Parameters 17.3. FIR Filter IP Operation 17.4. FIR Filter Interfaces 17.5. FIR Filter Registers 17.6. FIR Filter IP Software API
17.3. FIR Filter IP Operation x
17.3.1. FIR Filter Processing 17.3.2. FIR Filter Precision 17.3.3. FIR Coefficient Specification 17.3.4. FIR Filter Symmetry 17.3.5. Result to Output Data Type Conversion
17.3.4. FIR Filter Symmetry x
17.3.4.1. No Symmetry 17.3.4.2. Horizontal Symmetry 17.3.4.3. Vertical Symmetry 17.3.4.4. Horizontal and Vertical Symmetry 17.3.4.5. Diagonal Symmetry
18. Frame Cleaner Intel® FPGA IP x
18.1. About the Frame Cleaner IP 18.2. Frame Cleaner IP Parameters 18.3. Frame Cleaner IP Functional Description 18.4. Frame Cleaner IP Interfaces 18.5. Frame Cleaner IP Registers 18.6. Frame Cleaner IP Software API
18.1. About the Frame Cleaner IP x
18.1.1. Frame Cleaner IP Performance and Resources
19. Full-Raster to Clocked Video Converter Intel® FPGA IP x
19.1. About the Full-Raster to Clocked Video Converter 19.2. Full Raster to Clocked Video Converter Parameters 19.3. Full-Raster to Clocked Video Converter Block Description 19.4. Full-Raster to Clocked Video Converter Registers
19.1. About the Full-Raster to Clocked Video Converter x
19.1.1. Full-Raster to Clocked Video Converter Features 19.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
19.3. Full-Raster to Clocked Video Converter Block Description x
19.3.1. Full Raster to Clocked Video Converter Interfaces
20. Full-Raster to Streaming Converter Intel® FPGA IP x
20.1. About the Full-Raster to Streaming Converter IP 20.2. Full-Raster to Streaming Converter Parameters 20.3. Full-Raster to Streaming Converter Block Description
20.1. About the Full-Raster to Streaming Converter IP x
20.1.1. Full-Raster to Streaming Converter Features 20.1.2. Full-Raster to Streaming Converter Performance and Resources
20.3. Full-Raster to Streaming Converter Block Description x
20.3.1. Full-Raster to Streaming Converter Interfaces
21. Generic Crosspoint Intel® FPGA IP x
21.1. About the Generic Crosspoint IP 21.2. Generic Crosspoint IP Parameters 21.3. Generic Crosspoint IP Interfaces 21.4. Generic Crosspoint IP Registers 21.5. Generic Crosspoint IP Software API
21.1. About the Generic Crosspoint IP x
21.1.1. Generic Crosspoint IP Features 21.1.2. Generic Crosspoint Performance and Resources
22. Genlock Signal Router Intel® FPGA IP x
22.1. About the Genlock Signal Router IP 22.2. Genlock Signal Router IP Parameters 22.3. Genlock Signal Router IP Interfaces 22.4. Genlock Signal Router IP Registers 22.5. Genlock Signal Router IP Software API
22.1. About the Genlock Signal Router IP x
22.1.1. Genlock Signal Router IP Features 22.1.2. Genlock Signal Router IP Performance and Resources
23. Guard Bands Intel® FPGA IP x
23.1. About the Guard Bands IP 23.2. Guard Bands IP Parameters 23.3. Guard Bands IP Interfaces 23.4. Guard Bands IP Registers 23.5. Guard Bands IP Software API
23.1. About the Guard Bands IP x
23.1.1. Guard Bands IP Performance and Resources
24. Mixer Intel® FPGA IP x
24.1. About the Mixer IP 24.2. Mixer IP Parameters 24.3. Mixer IP Functional Description 24.4. Mixer IP Registers 24.5. Mixer IP Software API
24.1. About the Mixer IP x
24.1.1. Mixer IP Performance and Resources
24.3. Mixer IP Functional Description x
24.3.1. Mixer IP Interfaces
25. Pixels in Parallel Converter Intel® FPGA IP x
25.1. About the Pixels in Parallel Converter IP 25.2. Pixels in Parallel IP Converter Parameters 25.3. Pixels in Parallel Converter Interfaces 25.4. Pixels in Parallel Converter Registers 25.5. Pixels in Parallel Converter IP Software API
25.1. About the Pixels in Parallel Converter IP x
25.1.1. Pixels in Parallel IP Converter Performance and Resources
26. Scaler Intel® FPGA IP x
26.1. About the Scaler 26.2. Scaler IP Parameters 26.3. Scaler IP Functional Description 26.4. Scaler IP Registers 26.5. Scaler IP Software API
26.1. About the Scaler x
26.1.1. Scaler IP Performance and Resources
26.2. Scaler IP Parameters x
26.2.1. Updating Scaler IP Runtime Coefficients 26.2.2. Scaler Maximum Resolution
26.3. Scaler IP Functional Description x
26.3.1. Partial Frame Scaling 26.3.2. Scaler IP Interfaces
27. Tone Mapping Operator Intel® FPGA IP x
27.1. About the Tone Mapping Operator IP 27.2. TMO IP Parameters 27.3. TMO IP Block Description 27.4. TMO IP Registers 27.5. TMO IP Software API
27.1. About the Tone Mapping Operator IP x
27.1.1. TMO IP Features 27.1.2. TMO IP Performance and Resource Utilization
27.3. TMO IP Block Description x
27.3.1. TMO IP Interfaces 27.3.2. TMO IP Latency
28. Test Pattern Generator Intel® FPGA IP x
28.1. About the Test Pattern Generator IP 28.2. Test Pattern Generator IP Parameters 28.3. Test Pattern Generator IP Functional Description 28.4. Test Pattern Generator IP Registers 28.5. Test Pattern Generator IP Software API
28.1. About the Test Pattern Generator IP x
28.1.1. Test Pattern Generator IP Performance and Resources
28.3. Test Pattern Generator IP Functional Description x
28.3.1. Test Pattern Generator IP Interfaces
29. Video Frame Buffer Intel® FPGA IP x
29.1. About the Video Frame Buffer IP 29.2. Video Frame Buffer IP Parameters 29.3. Video Frame Buffer IP Functional Description 29.4. Video Frame Buffer IP Registers 29.5. Video Frame Buffer IP Software API
29.1. About the Video Frame Buffer IP x
29.1.1. Video Frame Buffer Performance and Resources
29.3. Video Frame Buffer IP Functional Description x
29.3.1. Video Frame Buffer IP Interfaces
30. Video Streaming FIFO Intel® FPGA IP x
30.1. About the Video Streaming FIFO IP 30.2. Video Streaming FIFO IP Parameters 30.3. Video Streaming FIFO IP Interfaces
30.1. About the Video Streaming FIFO IP x
30.1.1. Video Streaming FIFO IP Performance and Resources
31. Video Timing Generator Intel® FPGA IP x
31.1. About the Video Timing Generator IP 31.2. Video Timing Generator IP Parameters 31.3. Video Timing Generator IP Functional Description 31.4. Video Timing Generator IP Interfaces 31.5. Video Timing Generator IP Registers 31.6. Video Timing Generator IP Software API
31.1. About the Video Timing Generator IP x
31.1.1. Video Timing Generator IP Features 31.1.2. Video Timing Generator IP Performance and Resources
32. Warp Intel® FPGA IP x
32.1. About the Warp IP 32.2. Warp IP Parameters 32.3. Warp IP Block Description 32.4. Warp IP Registers 32.5. Warp IP Software API
32.1. About the Warp IP x
32.1.1. Warp IP Features 32.1.2. Warp IP Performance and Resource Utilization
32.3. Warp IP Block Description x
32.3.1. Warp IP Interfaces 32.3.2. Warp IP Latency 32.3.3. External Memory for Warp IP
32.5. Warp IP Software API x
32.5.1. Using Warp IP Software 32.5.2. Warp IP Software Code Examples
33. Design Security x
33.1. Memory Subsystems 33.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Resampler Intel® FPGA IP
11. Clipper Intel® FPGA IP
12. Clocked Video Input Intel® FPGA IP
13. Clocked Video to Full-Raster Converter Intel® FPGA IP
14. Clocked Video Output Intel® FPGA IP
15. Color Space Converter Intel® FPGA IP
16. Deinterlacer Intel® FPGA IP
17. FIR Filter Intel® FPGA IP
18. Frame Cleaner Intel® FPGA IP
19. Full-Raster to Clocked Video Converter Intel® FPGA IP
20. Full-Raster to Streaming Converter Intel® FPGA IP
21. Generic Crosspoint Intel® FPGA IP
22. Genlock Signal Router Intel® FPGA IP
23. Guard Bands Intel® FPGA IP
24. Mixer Intel® FPGA IP
25. Pixels in Parallel Converter Intel® FPGA IP
26. Scaler Intel® FPGA IP
27. Tone Mapping Operator Intel® FPGA IP
28. Test Pattern Generator Intel® FPGA IP
29. Video Frame Buffer Intel® FPGA IP
30. Video Streaming FIFO Intel® FPGA IP
31. Video Timing Generator Intel® FPGA IP
32. Warp Intel® FPGA IP
33. Design Security
34. Document Revision History for Video and Vision Processing Suite User Guide

15.5. Color Space Converter IP Software API

The IP includes software for run-time control. The IP does not fit any of the generic device models provided by the Nios II HAL and it exposes a set of dedicated accessors to the control and status registers. The IP driver structure inherits the base driver structure so all common methods defined in Video and Vision Processing IPs Software API are applicable.

Register definition header file: intel_vvp_csc_regs.h

Include file: intel_vvp_csc.h

Table 213.  Color Space Converter IP Software API
Name Description
intel_vvp_csc_init Initialize the Color Space Converter instance
Intel_vvp_core_* Accessors defined in Video and Vision Processing IPs Software Programming Model. Writable when Lite is on. Readable when Lite is off and Debug features is on.
intel_vvp_csc_get_lite_mode Returns if Lite mode is on
intel_vvp_csc_get_debug_enabled Returns if Debug features is on

intel_vvp_csc_get_bits_per_sample_in

Returns the number of input bits per color sample

intel_vvp_csc_get_bits_per_sample_out

Returns the number of output bits per color sample
intel_vvp_csc_are_coeffs_signed Returns if the nine coefficients have a sign bit and can be negative

intel_vvp_csc_get_coeffs_int_bits

Returns the number of integer bits (excluding sign bit) available to quantize coefficients
intel_vvp_csc_are_summands_signed Returns if the three summands have a sign bit and can be negative

intel_vvp_csc_get_summands_int_bits

Returns the number of integer bits (excluding sign bit) available to quantize summands

intel_vvp_csc_get_coeffs_frac_bits

Returns the number of fractional bits available to quantize both coefficients and summands
intel_vvp_csc_get_binary_point_right_move Returns the fixed scaling factor applied to values at the output of the IP
intel_vvp_csc_get_rounding_method Returns the method used to convert floating-point values back to integer values at the output of the IP
intel_vvp_csc_is_running Returns if the IP is currently processing video data
intel_vvp_csc_get_commit_status Returns if there are uncommitted writes
intel_vvp_csc_get_status Reads the status register
intel_vvp_csc_set_quantized_coeff_data Program the IP with a new set of quantized coefficients/summands
intel_vvp_csc_get_quantized_coeff_data Retrieve the set of quantized coefficients/summands programmed into the IP
intel_vvp_csc_set_coeff_data Program the IP with a new set of floating-point coefficients/summands
intel_vvp_csc_get_coeff_data Retrieve the set of floating-point coefficients/summands programmed into the IP
intel_vvp_csc_set_output_color_space Selects the current output color space (full mode)
intel_vvp_csc_get_output_color_space Returns the current output color space (full mode)
intel_vvp_csc_commit_writes Commit all outstanding writes

enum eIntelVvpCscRounding

Members

kIntelVvpCscRoundUp (1) – Rounding up (half up towards positive infinity)

kIntelVvpCscRoundHalfEven (2) – Rounding half to even (bankers’ rounding)

kIntelVvpCscRoundTruncate (3) – Truncation (no rounding)

kIntelVvpCscRoundInvalid (-1) – Invalid rounding method (used to indicate errors)

Description

Enumeration for the rounding method used by the IP

enum eIntelVvpCscColorSpace

Members

kIntelVvpCsRgb (0) – Rounding up (half up towards positive infinity)

kIntelVvpCsYcc (1) – Rounding half to even (bankers’ rounding)

kIntelVvpCsMono (2) – Truncation (no rounding)

kIntelVvpCscRoundInvalid (-1) – Invalid rounding method (used to indicate errors)

Description

Enumeration for the rounding method used by the IP

struct intel_vvp_coefficients

Members

struct { float c1; float c2; float c3; } coeffs[3]; – Matrix of 9 coefficients

float s[3] – Vector of 3 summands

Description

The coefficients and summands as floating-point values

struct intel_vvp_quantized_coefficients

Members

struct { int32_t c1; int32_t c2; int32_t c3; } coeffs[3]; – Matrix of 9 coefficients

int32_t s[3] – Vector of 3 summands

Description

The coefficients and summands as quantized integer values

intel_vvp_csc_init

Prototype 
 int intel_vvp_csc_init(intel_vvp_csc_instance *instance, intel_vvp_core_base base);
Description

Initializes a Color Space Converter instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match or if the register map version is not supported. Otherwise, the function proceeds to read and store the IP compile-time parameterization. The instance does not fully initialized and should not be used further by the application if returning a non-zero error code.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

base – base address of the register map

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID (0x6AF7).

kIntelVvpCorePidErr if the product_id does not match with the Color Space Converter product ID

kIntelVvpCoreInstanceErr if the instance is a null pointer

kIntelVvpCrsRegMapVersionErr if the register map is not supported

intel_vvp_csc_get_lite_mode

Prototype 
 bool intel_vvp_csc_get_lite_mode(intel_vvp_csc_instance *instance);
Description

Returns the value of the LITE_MODE register. The instance must be a valid intel_vvp_csc_instance fully initialized

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

true if the IP is parameterized in lite mode

intel_vvp_csc_get_debug_enabled

Prototype 
 bool intel_vvp_csc_get_debug_enabled(intel_vvp_csc_instance *instance);
Description

Returns the value of the DEBUG_ENABLED register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

true if the IP is parameterized with debug features enabled

intel_vvp_csc_get_bits_per_sample_in

Prototype 
 uint8_t intel_vvp_csc_get_bits_per_sample_in(intel_vvp_csc_instance *instance);
Description

Returns the value of the BPS_IN register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

the input bits per sample parameter used to generate the IP.

intel_vvp_csc_get_bits_per_sample_out

Prototype 
 uint8_t intel_vvp_csc_get_bits_per_sample_out(intel_vvp_csc_instance *instance);
Description

Returns the value of the BPS_OUT register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

the output bits per sample parameter used to generate the IP.

intel_vvp_csc_are_coeffs_signed

Prototype 
 bool intel_vvp_csc_are_coeffs_signed(intel_vvp_csc_instance* instance);
Description

Returns the value of the COEFFS_SIGNED register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

If signed coefficients have been allowed at IP generation time.

intel_vvp_csc_get_coeffs_int_bits

Prototype 
 uint8_t intel_vvp_csc_get_coeffs_int_bits (intel_vvp_csc_instance *instance);
Description

Returns the value of the COEFFS_INT_BITS register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

the number of integer bits set at IP generation time to parameterize the quantization of the coefficients

intel_vvp_csc_are_summands_signed

Prototype 
 bool intel_vvp_csc_are_summands_signed(intel_vvp_csc_instance* instance);
Description

Returns the value of the SUMMANDS_SIGNED register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

If signed summands have been allowed at IP generation time.

intel_vvp_csc_get_summands_int_bits

Prototype 
 uint8_t intel_vvp_csc_get_summands_int_bits (intel_vvp_csc_instance *instance);
Description

Returns the value of the SUMMANDS_INT_BITS register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

the number of integer bits set at IP generation time to parameterize the quantization of the summands

intel_vvp_csc_get_coeffs_frac_bits

Prototype 
 uint8_t intel_vvp_csc_get_coeffs_frac_bits (intel_vvp_csc_instance *instance);
Description

Returns the value of the FRAC_BITS register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

the number of fractional bits set at IP generation time to parameterize the quantization of the coefficients and summands

intel_vvp_csc_get_binary_point_right_move

Prototype 
 int8_t intel_vvp_csc_get_binary_point_right_move(intel_vvp_csc_instance *instance);
Description

Returns the value of the BINARY_POINT_RIGHT_MOVE register. The fixed scaling factor applied to the IP output samples and selected at IP generation time. Output values are scaled by 2^(binary_point_right_move). This is usually done to account for differences between bps_in and bps_out. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

The binary_point_right_move value selected at generation time

intel_vvp_csc_get_rounding_method

Prototype 
 eIntelVvpCscRounding intel_vvp_csc_get_rounding_method(intel_vvp_csc_instance *instance);
Description

Returns the value of the ROUND_METHOD register. The instance must be a valid intel_vvp_csc_instance fully initialized. This is the method to convert fixed-point values to integer values at the end of the CSC processing.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

The IP rounding method.

intel_vvp_csc_is_running

Prototype 
 bool intel_vvp_csc_is_running(intel_vvp_csc_instance* instance);
Description

Reads and returns the running bit of the STATUS register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

True is the IP is currently receiving/storing an input field, false when between two input fields

intel_vvp_csc_get_commit_status

Prototype 
 bool intel_vvp_csc_get_commit_status(intel_vvp_csc_instance* instance);
Description

Reads and returns the commit pending bit of the STATUS register. The instance must be a valid intel_vvp_csc_instance fully initialized and configured in full mode.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

True is the IP is configured in full mode and if the agent interface contains uncommitted writes.

intel_vvp_csc_get_status

Prototype 
 uint32_t intel_vvp_csc_get_status(intel_vvp_csc_instance* instance);
Description

Reads the STATUS register. The instance must be a valid intel_vvp_csc_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

The content of the STATUS register

intel_vvp_csc_set_quantized_coeff_data

Prototype 
 int intel_vvp_csc_set_quantized_coeff_data(intel_vvp_csc_instance* instance, const intel_vvp_quantized_coefficients* quantized_coeffs);
Description

Programs the IP with the set of coefficients and summands. The call checks for correctness of the quantized values and returns an error if invalid bits are set. Sign extension to the full 32 bit range is accepted. Quantization errors do not prevent the coefficients from being updated

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

quantized_coeffs – pointer to the structure containing the 9 quantized coefficients and summands

Returns

kIntelVvpCoreOk in case of success, negative error code otherwise

kIntelVvpCoreInstanceErr if the instance is invalid

kIntelVvpCoreNullPtrErr if quantized_coeffs is a NULL pointer

kIntelVvpCscQuantizationErr if the quantized coefficients/summands are out-of-range

intel_vvp_csc_get_quantized_coeff_data

Prototype 
 int intel_vvp_csc_get_quantized_coeff_data(intel_vvp_csc_instance* instance, intel_vvp_quantized_coefficients* quantized_coeffs)
Description

Reads and returns the current set of coefficients programmed in the IP. The instance must be a valid intel_vvp_csc_instance fully initialized and configured with debug enabled.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

quantized_coeffs – storage space to return the quantized coefficients

Returns

kIntelVvpCoreOk or a negative error code in case of error

kIntelVvpCoreInstanceErr, if the instance is invalid

kIntelVvpCoreNullPtrErr, if quantized_coeffs is the NULL pointer

intel_vvp_csc_set_coeff_data

Prototype 
 int intel_vvp_csc_set_coeff_data(intel_vvp_csc_instance* instance, const intel_vvp_coefficients* coeffs, int summand_rescale);
Description

Programs the IP with the set of coefficients and summands. The call quantizes the user-defined floating-point coefficients and returns an error if values are out-of-range. Quantization errors do not prevent the coefficients from being updated

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

coeffs – pointer to the structure containing the 9 floating-point coefficients and 3 summands

summand_rescale – scaling factor (2^summand_rescale) applied to the input summand values. Non-zero values are typically used when using a ready-made conversion table designed for a number of bits per color sample that does not match with the input bits per sample value used to parameterize the IP

Returns

kIntelVvpCoreOk in case of success, negative error code otherwise

kIntelVvpCoreInstanceErr if the instance is invalid

kIntelVvpCoreNullPtrErr if coeffs is a NULL pointer

kIntelVvpCscQuantizationErr if the coefficients/summands are out-of-range and cannot be quantized accurately

intel_vvp_csc_get_coeff_data

Prototype 
int intel_vvp_csc_get_coeff_data(intel_vvp_csc_instance* instance, intel_vvp_coefficients* coeffs)
Description

Reads and returns the current set of coefficients programmed in the IP. The instance must be a valid intel_vvp_csc_instance fully initialized and configured with debug enabled. Coefficients are converted back to floating-point values before being returned.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

coeffs – storage space to return the floating-point coefficients

Returns

kIntelVvpCoreOk or a negative error code in case of error

kIntelVvpCoreInstanceErr, if the instance is invalid

kIntelVvpCoreNullPtrErr, if coeffs is the NULL pointer

intel_vvp_csc_set_output_colorspace

Prototype 
 int intel_vvp_csc_set_output_colorspace(intel_vvp_csc_instance* instance, int8_t output_color_space);
Description

Writes the required output colorspace to the OUTPUT_CS register. The instance must be a valid intel_vvp_csc_instance fully initialized and configured in full mode.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

output_color_space – a colorspace code

Returns

kIntelVvpCoreOk or a negative error code in case of error

kIntelVvpCoreInstanceErr, if the instance is invalid

kIntelVvpCrsParamErr, if the output colorspace is invalid (<0)

intel_vvp_csc_get_output_colorspace

Prototype

int8_t intel_vvp_csc_get_output_colorspace(intel_vvp_csc_instance* instance);

Description 
 Reads the OUTPUT_CS register. The instance must be a valid intel_vvp_csc_instance fully initialized and configured in full mode with debug enabled.
Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

the last value written to the OUTPUT_CS register, negative value in case of errors

intel_vvp_csc_commit_writes

Prototype 
int intel_vvp_csc_commit_writes(intel_vvp_csc_instance* instance)
Description

Commits all pending writes before processing the next field. The instance must be valid and parameterized in full mode.

Arguments

instance – pointer to the intel_vvp_csc_instance software driver instance structure

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise

Related Information
Level Two Title