Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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Document Table of Contents

17.1. About the FIR Filter

The FIR Filter Intel FPGA IP performs 2D convolutions using matrices of specific coefficients.

The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The FIR filter IP takes input resolution information from image information packets or using the register interface for lite variants.

An Avalon memory-mapped interface allows you to read the running status of the IP. This interface is mandatory for lite variants.