Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.3.2. 3D LUT IP Latency

The latency information can predict the approximate latency between the input and the output of your video processing pipeline.
Table 37.  3D LUT IP operation mode latencyThe table shows latency as a number of valid clock cycles. Intel measures the latency assuming that other functions on the datapath are not stalling the IP, i.e. the output ready signal is high.
Device Latency (cycles)

Intel Arria 10

Intel Cyclone 10 GX

21

Intel Agilex

Intel Stratix 10

22