Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022
Public

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1.5. Glossary of Video and Vision Terminology

Table 3.  Glossary of Video and Vision Terminology
Agent Part of a memory-mapped interface, which receives transactions from a host interface.
Auxiliary control packets A term for any Intel FPGA streaming video protocol control packet with ID>=2. Optionally available to use for a variety of purposes, such as timestamping, register updates, IP synchronization and non-video data such as closed-captioning.
Avalon streaming interface Intel streaming standard, similar to AXI4-Stream. Used by VIP IPs.
Avalon memory-mapped interface Intel memory-mapped interface standard, similar to AXI4-Lite.
Field Either a progressive frame of video, or a field of interlaced video.
Frame A progressive frame of video.
Full variant The variant of the IPs when you turn off Lite mode of the Intel FPGA streaming video protocol and which comprises both control and data packets.
Full-raster variant The variant of the IP of the Intel FPGA streaming video protocol that comprises both blanking and active data packets.
Host Part of a memory-mapped interface, which sends transactions to one or more agent interfaces.
Interlaced Interlaced video comprises alternating fields with either the odd or even lines comprising a video frame. A 1080i video comprises one field of 540 odd-numbered lines followed by one field of 540 even-numbered lines.
Lite variant The variant of the IPs when you turn on lite mode for the Intel FPGA streaming video protocol and which comprises only data packets.
Metapackets Either an image information packet, an end-of-field packet, or an auxiliary control packet.
Progressive Video that is not interlaced. Lines are transmitted in order.
Symbol Pixels are comprised of 1 to 4 symbols. A symbol comprises between 8 and 16 bits of data, representing one color from an RGB triplet (red, blue, green) or a luma or chroma sample from YCbCr pixels, or some other color space component.
Undefined behavior If an IP experiences a stimulus that falls outside of its design parameters, its behavior is unspecified. The IP may fail gracefully, or lock-up, or continue working. Intel does not specify the outcome.
VIP Video and image processing. Intel’s previous generation of video processing IPs from the Video and Image Processing Suite.