Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022
Public

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Document Table of Contents

18.4. Frame Cleaner IP Interfaces

Table 240.  Frame Cleaner IP Interfaces
Signal name Direction Width Description
Clocks and resets
main_clock_clk in 1 AXI4-S processing clock.
main_reset_rst in 1 AXI4-S processing reset.
agent_clock_clk in 1 Clock for the Avalon memory-mapped control agent interface. Only if you select Separate clock for control interface
agent_reset_rst in 1 Reset for the Avalon memory-mapped control agent interface. Only if you select Separate clock for control interface
Control interfaces
av_mm_control_agent_address in 7 Avalon memory-mapped agent address
av_mm_control_agent_write in 1 Avalon memory-mapped agent write
av_mm_control_agent_writedata in 32 Avalon memory-mapped agent write data
av_mm_control_agent_byteenable in 4 Avalon memory-mapped agent byte enable
av_mm_control_agent_read in 1 Avalon memory-mapped agent read
av_mm_control_agent_readdata out 32 Avalon memory-mapped agent read data
av_mm_control_agent_readdatavalid out 1 Avalon memory-mapped agent read
av_mm_control_agent_waitrequest out 1 Avalon memory-mapped agent wait request

Intel FPGA streaming video interfaces

axi4s_vid_in_tdata in 43 AXI4-S data in
axi4s_vid_in_tvalid in 1 AXI4-S data valid
axi4s_vid_in_tuser in

AXI4-S tuser

tuser[0] indicates start of video frame when asserted

tuser[1] indicates the start of a non-video packet when asserted

axi4s_vid_in_tlast in 1 AXI4-S end of packet
axi4s_vid_in_tready out 1 AXI4-S data ready
axi4s_vid_out_tdata out 0 AXI4-S data in
axi4s_vid_out_tvalid out 1 AXI4-S data valid
axi4s_vid_out_tuser out 44

AXI4-S tuser

tuser[0] indicates start of video frame when asserted

tuser[1] indicates the start of a non-video packet when asserted

axi4s_vid_out_tlast out 1 AXI4-S end of packet
axi4s_vid_out_tready in 1 AXI4-S data ready
43

The equation gives all tdata widths in these interfaces:

max (ceil((bits per color sample x number of color planes) / 8) x pixels in parallel x 8, 16)

44

The equation gives all tuser widths in these interfaces

N = ceil (tdata width / 8)