Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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Document Table of Contents

22.1.1. Genlock Signal Router IP Features

  • An Avalon memory-mapped control interface

    1 to 32 clocked video input interfaces

    Three input clocked video interfaces:

    • Intel clocked video
    • full-raster (refer to Intel FPGA Streaming Video Protocol Specification)
    • Clock only
  • Synchronous and asynchronous clocked video input signals
  • Five user configurable timing control extract modes:
    • Intel clocked video blank or sync timing
    • full-raster blank or sync timing
    • Genlock discrete field, vertical, and horizontal timing signals, and clocks only output interface
  • Three user configurable frame sync extract modes:
    • full-raster TUSER start of frame timing
    • Field toggle
    • Field pulse
  • Processor configurable genlock router switching between input and output ports

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