Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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19.3. Full-Raster to Clocked Video Converter Block Description

The IP passes the pixel and timing data through unmodified. The streaming full-raster bus encapsulates all the pixel and timing data on a single bus, tData. The clocked video bus is a bundle of multiple single wires for the individual video timing strobes, and a data bus for the pixel data.

The clocked video bus can contain additional side-band signals, such as discrete 16-bit signals for the width and height of the raster. The IP ignores these side-band signals. The IP copies some signals from CPU registers. The sideband signals provide backward IO interface compatibility between this IP and legacy Intel clocked video input and clocked video output interfaces.

Figure 50. High-level mapping from streaming full-raster to clocked video format

The figure shows how mapping separates the discrete signals used by the clocked video protocol from the single AXI4-S tData bus. You need a processor interface to construct the legacy Intel clocked video input and clocked video output signals.