Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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Document Table of Contents

33.1. Memory Subsystems

Some video and vision IPs require you to connect them to RAM. Configuring these blocks requires you to set a base address. Other configuration options determine the RAM space the IP requires. These two elements define the address space the IP operates over. The IPs only use the address space defined by these parameters. You should appropriately map modules in the address space of the system. You should implement any access control protections associated with the memory subsystem. The IPs do not perform any system configuration checks. Platform Designer performs some limited system configuration checks, which may or may not be sufficient according to the complexity of requirements.