Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022
Public

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4. Video and Vision Processing IP Interfaces

The IPs have the main clock, an optional control clock, and some IPs have an optional memory interface clock.
Table 6.   Intel FPGA video stream input interface
Signal name Direction AXI4-Stream Wire Signal Width
axi4s_vid_in_tdata Input TDATA Number of data bytes * 8
axi4s_vid_in_tlast Input TLAST 1
axi4s_vid_in_tuser Input TUSER Number of data bytes
axi4s_vid_in_tvalid Input TVALID 1
axi4s_vid_in_tready Output TREADY 1
Table 7.   Intel FPGA video stream output interface
Signal name Direction AXI4-Stream Wire Signal Width
axi4s_vid_out_tdata Output TDATA Number of data bytes * 8
axi4s_vid_out_tlast Output TLAST 1
axi4s_vid_out_tuser Output TUSER Number of data bytes
axi4s_vid_out_tvalid Output TVALID 1
axi4s_vid_out_tready Input TREADY 1

Number of data bytes = max(2, ceil(bits per sample * number of color planes / 8) * pixels in parallel)