Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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Document Table of Contents

8.3.1. 3D LUT IP Interfaces

The IP has three functional interfaces.
The interfaces are:
  • Intel FPGA video stream input interface
  • Intel FPGA video stream output interface
  • Avalon Memory-Mapped compatible CPU interface

The 3D LUT IP control interface uses Avalon Memory-Mapped protocol to access control and RAM interface registers.


The 3D LUT IP has two clock domains, each with a corresponding reset signal.

Table 35.  Clock domains
Clock name Description
cpu_clock CPU interface clock domain
vid_clock Video processing clock domain

The CPU interface uses little bandwidth and therefore does not impose a minimum clock frequency. The video clock frequency depends on the video resolution, frame rate, and the 3D LUT IP’s number of pixels in parallel. For example, a 300 MHz clock at 2 pixels in parallel supports active video resolutions up to 4096x2160 at 60 Hz.

All RTL-based blocks that transfer or receive data from a different clock domain include clock domain crossing (CDC) circuits for both, single bit and data bus signal cases. The CDC safely allows exchange of data between the two asynchronous clock domains. This principle applies to the control signals from the CPU interface to the main video datapath. The 3D LUT IP includes a .sdc file to constrain this CDC.


Table 36.  Resets associated with clock domainsBoth resets are synchronous active-high
Reset name Description
cpu_reset CPU interface clock domain reset.
vid_reset Video processing clock domain reset.