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Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Resampler Intel® FPGA IP
11. Clipper Intel® FPGA IP
12. Clocked Video Input Intel® FPGA IP
13. Clocked Video to Full-Raster Converter Intel® FPGA IP
14. Clocked Video Output Intel® FPGA IP
15. Color Space Converter Intel® FPGA IP
16. Deinterlacer Intel® FPGA IP
17. FIR Filter Intel® FPGA IP
18. Frame Cleaner Intel® FPGA IP
19. Full-Raster to Clocked Video Converter Intel® FPGA IP
20. Full-Raster to Streaming Converter Intel® FPGA IP
21. Generic Crosspoint Intel® FPGA IP
22. Genlock Signal Router Intel® FPGA IP
23. Guard Bands Intel® FPGA IP
24. Mixer Intel® FPGA IP
25. Pixels in Parallel Converter Intel® FPGA IP
26. Scaler Intel® FPGA IP
27. Tone Mapping Operator Intel® FPGA IP
28. Test Pattern Generator Intel® FPGA IP
29. Video Frame Buffer Intel® FPGA IP
30. Video Streaming FIFO Intel® FPGA IP
31. Video Timing Generator Intel® FPGA IP
32. Warp Intel® FPGA IP
33. Design Security
34. Document Revision History for Video and Vision Processing Suite User Guide
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Ixiasoft
9.3. AXI-Stream Broadcaster IP Interfaces
Name | Direction | Width | Description |
---|---|---|---|
Clocks and Resets | |||
vid_clock | In | 1 | AXI4-S processing clock |
vid_reset | In | 1 | AXI4-S processing reset |
Intel FPGA streaming video interfaces | |||
axi4s_vid_in_tdata | In | 6 | AXI4-S data in |
axi4s_vid_in_tvalid | In | 1 | AXI4-S data valid |
axi4s_vid_in_tuser[0] | In | 1 | AXI4-S start of video frame |
axi4s_vid_in_tuser[1] | In | 1 |
|
axi4s_vid_in_tuser[N-1:2] | In | 7 | Unused |
axi4s_vid_in_tlast | In | 1 | AXI4-S end of packet |
axi4s_vid_in_tready | Out | 1 | AXI4-S data ready |
axi4s_vid_out_x_tdata | Out | 6 | AXI4-S data out |
axi4s_vid_out_x_tvalid | Out | 1 | AXI4-S data valid |
axi4s_vid_out_x_tuser[0] | Out | 1 | AXI4-S start of video frame |
axi4s_vid_out_x_tuser[1] | Out | 1 |
|
axi4s_vid_out_x_tuser[N-1:2] | Out | 7 | Unused |
axi4s_vid_out_x_tlast | Out | 1 | AXI4-S end of packet |
axi4s_vid_out_tready | In | 1 | AXI4-S data ready |
Related Information
6
The equation gives the TDATA width for these interfaces for full or lite variants:
max (floor(((bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)
The equation gives the TDATA width for these interfaces for full-raster variants:
max (floor(((bits per color sample x (number of color planes + 1) x pixels in parallel) + 7) / 8) x 8, 16)
7 This equation gives the TUSER width N for these interfaces: ceil (tdata width / 8)