Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022
Public

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22.2. Genlock Signal Router IP Parameters

The IP offers compile-time parameters.
Table 296.  Genlock Signal Router IP Parameters
Parameter Values Description
Build configuration
Length of clock pulse 1 to 32 The number of clocks for the output genlock pulse
Number of genlock inputs 1 to 32 The number of input ports
Number of genlock outputs 1 to 32 The number of output ports
General-purpose input conduit True or false Turn on a general-purpose input port for this IP
Number of bits of GPI 1 to 32 The number of bits for the general-purpose input interface
General-purpose output conduit True or false Turn on a general-purpose output port for this IP
Number of bits of GPO 1 to 32 The number of bits for the general-purpose output interface
Genlock output type Discrete timing signals, Clocks only Select the type for all available outputs
Genlock Input Type: AXI-S FR (Per Input Interface)
Number of bits per color plane 8 to 16 The number of bits per color sample at the input
Number of pixels in parallel 1 to 8 The number of pixels transmitted every clock cycle.
Number of color planes 1 to 4 The number of color planes per pixel
AXI4-S FR interface TREADY True or false Enable the TREADY signal as part of the full-raster interface
Genlock Input Type: Discrete timing Clocked Video signals (Per Input Interface)
Clock 0 to 1 Discrete input interface has Input clock signal
F 0 to 1 Discrete input interface has Input field signal
V 0 to 1 Discrete input interface has Input vertical blanking signal
H 0 to 1 Discrete input interface has Input horizontal blanking signal
V sync 0 to 1 Discrete input interface has Input vertical sync signal
H sync 0 to 1 Discrete input interface has Input horizontal sync signal
Toggle 0 to 1 Discrete input interface has Input field pulse signal
Pulse 0 to 1 Discrete input interface has Input field toggle signal
Figure 55. Genlock Signal Router IP GUI