Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

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Document Table of Contents

22.1. About the Genlock Signal Router IP

The IP is a multichannel genlock strobe extractor and router. This IP passes genlock timing signals to internal or external FPGA multirate video clock generators. The IP helps video input and output clock genlock and frame synchronization, based on video timing markers derived from video connectivity IPs.
Figure 54. Genlock Signal Router IP Block Diagram

Data is input to and output from the Genlock Signal Router IP via a selectable number of ports. The final number of input and output ports, which is in the range 1 through 32 inclusive, can be configured via a Genlock Signal Router IP GUI.

At build time, you can configure the input port interfaces in three different modes: Intel video streaming full-raster, Intel clocked video, and clock only mode. The IP automatically extracts timing information from the input signals, and then routes the signals between the input and output ports. You can control the input-to-output routing dynamically at run-time using the processor interface.

The output interface for this IP provides two optional interfaces:

  • An interface with a set of discrete timing signals, such as field flag, horizontal, and vertical synchronization timing markers.
  • An interface that provides clocks only ports

The timing markers can then pass to internal or external FPGA multirate video clock generators.