Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 8/08/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.1. About the Clocked Video Output IP

The Clocked Video Output Intel FPGA IP merges the pixel data from an AXI4-S lite or AXI4-S full video bus with the real-time video signals from a reference AXI4-S full-raster stream. The output is an AXI4-S full-raster bus that you can connect directly to the Intel Interconnect IP.

Another IP can provide the reference AXI4-S full-raster stream or an embedded Video Timing Generator Intel FPGA IP can generate the reference stream.

Second Input Fall Back

The IP provides an optional second AXI4-S Video Streaming input. If the primary input stream fails, the IP automatically changes to use the second input. If the second input also fails, or is not used, the IP produces black. You can configure the exact pixel value for black at build time and via the processor interface at runtime.

By default, when the primary video input relocks to the timing reference the IP automatically changes back to the primary video input at the start of the next frame. However, you can change the default behavior via the processor interface. Using the processor interface, you can manually control when the IP changes from the test pattern input back to the video input. You can force the IP to select either the main video input, the test pattern input, or black.

Pixels in Parallel Support

The IP supports any number of pixels in parallel from 1 to 8. The raster dimensions have no restrictions on the number of pixels in parallel. The raster width does not have to be an integer multiple of pixels in parallel.

The pixel input stage contains a barrel shift to align the AXI4-S lite or AXI4-S full streams with the AXI4-S full-raster stream.

Did you find the information on this page useful?

Characters remaining:

Feedback Message