Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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3.7.2. Viewing NoC Elements in Chip Planner

NoC elements are also visible in the Intel® Quartus® Prime Chip Planner. The Chip Planner simplifies floorplanning by allowing you to view and constrain design logic within a visual display of the FPGA chip resources. You can use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter. You can also make assignment changes, such as creating and deleting Logic Lock, clock region, and resource assignments.

The NoC elements appear in Chip Planner as a row of boxes between the main logic array, the GPIO-B, and other blocks across the top and bottom edge of the die. You can also click Report Resources in the Chip Planner Tasks pane to locate different types of NoC resources, such as the following

  • NOC_INITIATOR
  • NOC_TARGET
  • NOC_AXILITE_INITIATOR
  • NOC_AXILITE_TARGET
  • NOC_PLL
  • NOC_SSM

Viewing your design in Chip Planner provides insight into how the Fitter physically arranges the NoC elements on the device. For general information about using the Chip Planner, refer to the Intel® Quartus® Prime Pro Edition User Guide: Design Optimization.

Figure 54. NoC Group Node in Chip Planner