Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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7.2.2. NoC Clock Control Intel FPGA IP Interfaces

Interfaces for NoC Clock Control FPGA IP describes the interfaces on the NoC Clock Control Intel FPGA IP. There are no RTL connections between the NoC Clock Control Intel FPGA IP and the hard memory NoC. Rather, you specify these connections using assignments in the NoC Assignment Editor, as Making NoC Assignments describes.

Table 26.  Interfaces for NoC Clock Control FPGA IP
Port Name Width Direction Description
refclk 1 Input Reference clock for NoC PLL
pll_lock_o 1 Output Lock signal for NoC PLL