Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
Document Table of Contents
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3.1.1. NoC Design Flow Options

The Intel® Quartus® Prime software supports the following two flows for NoC design:
  • Platform Designer Connection Flow—you use Platform Designer to configure and instantiate your NoC-related IP. You also use Platform Designer to make connections between NoC initiator bridges and NoC target bridges and to define the addressing mapping for these connections. Once you generate HDL for your Platform Designer system, your design is ready for RTL simulation. You must use the NoC Assignment Editor to create additional assignments, such as specifying NoC groupings and optional performance targets. You can use Interface Planner to make physical location assignments for your NoC elements. Then you compile your design and review the results.
  • NoC Assignment Editor Connection Flow—you can configure and instantiate your NoC-related IP in either Platform Designer or directly in RTL. You then use the NoC Assignment Editor to make all NoC assignments including grouping, connectivity, address mapping, and optional performance targets. After completing the assignments and rerunning Analysis & Elaboration, your design is ready for RTL simulation. You can use Interface Planner to make physical location assignments for your NoC elements. Then compile your design and review the results.

The NoC design flow that you select impacts the NoC design entry method, how you specify NoC connectivity and addressing assignments, and at what stage you can perform RTL simulation of the NoC. Subsequent stages of the design flow, such as assigning physical locations, compiling, and reviewing results, are the same in both flows.

Table 5.  Comparison of Platform Designer Connection Flow and NoC Assignment Editor Connection Flow
Design Steps Platform Designer Connection Flow NoC Assignment Editor Connection Flow
Configure NoC-related IP Parameter Editor launched from Platform Designer Parameter Editor launched from either Platform Designer or IP Catalog
Instantiate NoC-related IP in your design Platform Designer only Either Platform Designer or directly in RTL
Connect NoC initiator bridges and NoC target bridges Platform Designer NoC Assignment Editor
Define address maps for NoC connections Platform Designer NoC Assignment Editor
Specify NoC grouping NoC Assignment Editor
Specify NoC performance targets NoC Assignment Editor
Assign physical locations Interface Planner
Compile design and review results Intel® Quartus® Prime Pro Edition
Ready for RTL simulation After generating HDL in Platform Designer After completing NoC Assignment Editor and running Analysis & Elaboration