Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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Document Table of Contents
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3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator

Example 2 represents a single AXI4 manager in the fabric communicating to two external memory interfaces.

Example 2 contains two instances of the External Memory Interfaces (EMIF) IP and two instances of the NoC Initiator Intel FPGA IP:

  • The first initiator has a single AXI4 interface, and connects to the main AXI4 target interface of each external memory interface.
  • The second initiator has a single AXI4-Lite interface and connects to the sideband AXI4-Lite interface of each external memory interface.

The AXI4 initiator interface uses an address of 0x000000000 for the first memory interface, and an address of 0x100000000 for the second memory interface. The AXI4-Lite initiator interface uses an address of 0x0000000 for the first memory sideband interface, and an address of 0x8000000 for the second memory sideband interface.

The example also contains one instance of the NoC Clock Control Intel FPGA IP, but the AXI4-Lite interface is unconnected.