Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
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2.2. NoC Segments

Aside from the NoC PLL and SSM, the hard memory NoC also consists of segments containing initiators, targets, and switches. The structure of segments within the hard memory NoC depend on the interfaces with which they interact. Figure 2. Intel Agilex® 7 M-Series Device Layout shows the arrangement of these segments within each hard memory NoC.

The following section describes the individual NoC segments. The hard memory NoC along the top edge of the device contains 20 NoC initiators facing the FPGA fabric and 2 NoC initiators in the MPFE to interact with the HPS. The hard memory NoC along the bottom edge of the device contains 22 NoC initiators facing the FPGA fabric.

There is an additional service network running parallel to the main switch network within each hard memory NoC. This service network connects NoC SSM and the HPS AXI4 Lite initiator to AXI4 Lite targets. Fabric-facing NoC initiators can send transactions over the main network to the NoC SSM to access the service network for sideband configuration and system monitoring. The following NoC Segment diagrams do not show this service network.