Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
Document Table of Contents
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2.5.1. AXI4 Protocol Support

Intel Agilex® 7 M-Series FPGAs use AXI4 protocol for NoC initiators and NoC targets processing user read and write transaction requests and responses. The AMBA AXI4 in the hard memory NoC is fully compliant with the AXI4 specification, except for the following functions because there are no caches in the hard memory NoC or associated memory controllers.:

  • AxREGION
  • AxCACHE
  • AxLOCK is ignored
  • Only two AxQOS bits are honored
  • AxPROT is ignored
  • AxREGION and AxCACHE do not need to be provided by a compliant AXI4 implementation
  • For AxBURST, NoC targets, such as HBM2e and external memory controllers, support incrementing burst only. Refer to NoC Initiator Intel FPGA IP Interfaces.