Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
Document Table of Contents
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3.5.4.3.1. Example 3: Platform Designer Connection Flow

The following figures show how the Platform Designer System View and Address Map tabs display the connections and addressing in Example 3.

For simplicity, the System View in the following figures applies the Hide Clocks and Resets filter.

Figure 33. Platform Designer Connection Flow—System View for Example 3


Figure 34. Platform Designer Connection Flow—Address Map for Example 3