Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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2.5.3. Quality of Service (QoS) Support

Quality of Service (QoS) is a technique that the hard memory NoC uses to provide control of arbitration choices that satisfy performance requirements. You can also use QoS to prioritize some traffic. You can change this prioritization dynamically, or set this prioritization during configuration. To achieve system goals, system architects can use the QoS settings to specify the relative priority of traffic flows.

One can categorize initiator generated traffic into the following groups, according to sensitivity to latency:

Table 2.  Initiator-Generated Traffic Types
Traffic Type Description
Real-Time NoC initiators in this group are very sensitive to long-term and short-term latency, and fail when their buffers become empty. Examples include video display traffic and real-time applications. A video display engine must be able to fetch graphic data within a bounded amount of time to display images correctly on a monitor. Failing to meet real-time requirements may result in corrupt pixels or degradation of image sharpness or loss of screen synchronization.
Latency Sensitive The performance of this application type is directly linked to the latency of access. For example, in a CPU, processing can stop for many cycles when there is a cache miss.
Best Effort NoC initiators in this group can tolerate delays that other traffic causes and are insensitive to latency. These NoC initiators consume the remaining bandwidth, and must not interfere with real-time or latency-sensitive traffic. For example, file transfer or file download applications can stall without compromising the experience.

AXI QoS determines the associated NoC QoS. Urgency level is the priority of traffic within the NoC subsystem. A system can have multiple priority levels for traffic going to and from the memory.

You can configure the NoC Initiator Intel FPGA IP to use AXI4 QoS signals to determine the associated NoC QoS, or to send all NoC traffic with a fixed priority. If you configure the NoC Initiator Intel FPGA IP to use a fixed NoC priority, you can specify separate priorities for read and write traffic.

You can choose to specify the QoS Generator priority levels when parameterizing the NoC Initiator Intel FPGA IP. The priority levels are not run-time programmable. For more information on the QoS Generator in the NoC Initiator Intel FPGA IP, refer to NoC Initiator Intel FPGA IP.

Figure 12. Options for Generating Quality of Service: QoS Generator vs. AxQOS


Table 3. Memory Priority Versus QoS Settings shows the mapping of QoS signals to the urgency value of the corresponding packets. The NoC subsystem has four priority levels (urgency = 0, 1, 2 or 3). Within the NoC subsystem, traffic with priority level zero (0) has the lowest priority, while traffic with priority level 3 has the highest priority. While the external memory interface Hard Memory Controller supports up to four priority levels, HBM2e Hard Memory Controller supports only two priority levels. Best effort traffic should have a default urgency level of zero (0), with higher urgency levels reserved for real-time and latency-sensitive traffic. Note that only the top two bits of the AXI command QoS (arqos or awqos) map to a NoC quality-of-service option. The remaining bits are unused.

Table 3.  Memory Priority Versus QoS Settings
QoS[1:0] Urgency Level External Memory Priority Level HBM2e Priority Level

2’b00

0

0

0

2’b01

1

1

0

2’b10

2

2

1

2’b11

3

3

1