Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
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7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals

Clock and reset signals are separate for AXI4 and AXI4 Lite interfaces. Additionally, if you configure the IP with the unequal read and write widths, the clock and reset signals are separate for the AXI4 read-only and AXI4 write-only interfaces. When you choose an AXI4 Data Mode that is 512 or 576 bits wide, and also enable a separate clock for the NoC initiator hardware, the NoC Initiator Intel FPGA IP exposes an input named noc_bridge_fabric_clk.

Depending on IP configuration, prefixes may be s_axi4_, s_ro_axi4_, s_wo_axi4_, or s_axi4lite_. If you configure the IP for separate clock and reset signals for each interface, prefixes may be s<x>_woaxi4_aclk, s<x>_ro_axi4_aclk, s<x>_wo_axi4_, or s<x>_axi4lite_.