3.3.3. NoC Initiators for Fabric AXI4 Managers
Configure hard memory NoC initiators for fabric AXI4 managers using the NoC Initiator Intel FPGA IP in either IP Catalog or Platform Designer. Access the NoC Initiator Intel FPGA IP in the IP Catalog by expanding the Intel FPGA Interconnect category, and then expanding the NoC subcategory.
The NoC Initiator Intel FPGA IP allows the creation of multiple AXI4 and AXI4 Lite interfaces using the same configuration that interfaces to the same hard memory NoC subsystem. If your design requires NoC initiators with different configurations, or if your design uses both hard memory NoC subsystems along the top edge and bottom edge of the die, this configuration requires separate NoC Initiator Intel FPGA IP. Each AXI4 interface in the NoC Initiator Intel FPGA IP maps to one hard memory NoC initiator bridge.
In the IP parameter editor, you specify the following parameters for the IP instance:
- Specify a value for the Number of AXI4 interfaces and Number of AXI4 Lite interfaces. Each AXI4 interface is associated with its own physical NoC initiator bridge. AXI4 Lite interfaces, used to access control and status registers of NoC peripherals, are associated with the first physical NoC initiator bridge. If an instance of the NoC initiator IP has the number of AXI4 interfaces set to 0, that instance uses only one NoC initiator bridge that carries the AXI Lite transactions from all the exposed AXI Lite interfaces.
- Specify whether the AXI4 and AXI4 Lite interfaces have per-interface clock and reset signals, or whether the interfaces share these signals. If you do not configure for per-interface clock and reset signals, the IP exposes a single shared clock sink and reset sink interface for all AXI4 interfaces, and exposes a separate shared clock sink and reset sink for all AXI4 Lite interfaces.
- Select the data width for read and write interfaces using the AXI4 Data Mode parameter. Selections with read data width of 512 or 576 bits implement the fabric NoC to transport read response data directly into M20K memory blocks. If you select data widths of 288 or 576 bits, the AXI4 WUSER and RUSER signals carry the extra data bits.
- When using a 512 or 576 bit wide data mode, additionally specify whether the wide interfaces use an independent clock from the 256-bit NoC initiator hardware. Enable this option for best system-level performance when using wide data modes.
- Use the AXI4 interface handshaking parameter to optimize the interface handshaking for either fMAX or area. AXI4 Handshaking Support describes this option.
- Use the NoC QoS Mode parameter to specify whether AXI4 priority applies individually on each AXI4 transaction (AXI QoS option), or hard codes a single priority level into each interface (NOC Bridge generated option). For QoS details, refer to Quality of Service (QoS). If using the NoC Bridge generated option, additionally select the hard-coded values for NoC priority for Reads and NoC priority for Writes.
For example, Figure 20. Parameter Editor for NoC Initiator Intel FPGA IP shows the following NoC Initiator Intel FPGA IP configuration:
- The IP instance has 16 AXI4 interfaces and 0 AXI4 Lite interfaces.
- The AXI4 read and write channels are configured for 512-bit wide transactions. Since the interface is symmetrical, one AXI interface is exposed, which includes all 5 AXI channels (R, AR, W, AW, B).
- Configuration with an AXI4 data mode using 512 bit data paths indicates this IP is implemented using the fabric NoC.
- Clock(s) of wide read and write AXI channels are independent from the NoC initiator hardware clock. As a result, the read channels (R, AR) are implemented on the NOC clock domain, while the write channels (W, B, AW) use a different clock (noc_bridge_fabric_clk). This independence allows faster clocking of the INIU-facing portion of the write path. However, regardless of the value of this option, the user-facing AXI interface is clocked from the user clock (s0_axi4_clock).
- This IP uses the default AXI standard for interface handshaking (Fmax optimized). The NoC urgency level of each transaction is based on the AXI AxQOS value associated with each read or write command.
For full details on the NoC Initiator Intel FPGA IP, refer to NoC Initiator Intel FPGA IP