Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals

In the Platform Designer view of the NoC Clock Control Intel FPGA IP, there is an additional AXI4 NoC subordinate port. If you are using the early RTL simulation flow, you can connect this port to an AXI4 NoC manager port to specify an initiator-to-target connection in the Platform Designer System View tab. Platform Designer uses this connection when generating the simulation registration include file. You can now locate AXI4 NoC manager ports in the NoC Initiator Intel FPGA IP. For more information on the early RTL simulation flow, refer to Simulating NoC Designs.

If you are not using the early RTL simulation flow, you can leave the AXI4 NoC subordinate port unconnected in Platform Designer. Regardless of whether you connect the AXI4 NoC subordinate port in Platform Designer, the generated HDL for your system does not show the AXI4 NoC subordinate port on the NoC Clock Control Intel FPGA IP.

If you are designing your NoC system in RTL, the NoC Clock Control Intel FPGA IP does not have an AXI4 NoC subordinate port.