Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
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3.4.4. Connectivity Guidelines: NoC Clock Control

The NoC Clock Control Intel FPGA IP contains the NoC PLL and NoC SSM. Connect the refclk pin of this IP to a top-level port in your design, and to a high-quality clock source on your board.

  • If you are using the Platform Designer connection flow, as NoC Design Flow Options describes, instantiate your NoC IP in Platform Designer. The NoC Clock Control Intel FPGA IP has one AXI4 NoC subordinate interface that is an AXI4 Lite target that you can connect to NoC initiators. Connect this AXI4 Lite target to a NoC Initiator Intel FPGA IP that has an AXI4 Lite interface. to allow access to the NoC performance monitors. After connecting AXI4 NoC manager and AXI4 NoC subordinate interfaces, click to the Address Map tab, to specify the base address for each connection. If an AXI4 NoC manager interface connects to multiple AXI4 NoC subordinate interfaces, ensure each connection has a unique starting address. You can click the Assign Base Addresses button to allow Platform Designer to assign addresses automatically.
  • If you are using the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, and using Platform Designer to instantiate your NoC IP, do not connect the AXI4 NoC subordinate interface in the Platform Designer System View tab. After running Intel® Quartus® Prime Analysis & Elaboration, you can use the NoC Assignment Editor to define connectivity and addressing to prepare your design for RTL simulation.
  • If you are using the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, and instantiating your NoC IP directly in RTL, the AXI4 NoC subordinate interface does not exist. After running Intel® Quartus® Prime Analysis & Elaboration, you can use the NoC Assignment Editor to define connectivity and addressing to prepare your design for RTL simulation.