Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs 3. NoC Design Flow in Intel® Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Intel Agilex® 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

2.1. High-Level Architecture

Intel Agilex® 7 M-Series FPGAs provide two hard memory NoC subsystems that run horizontally along the top and bottom edges of the FPGA die. These subsystems are completely independent, and each subsystem interfaces with a separate set of peripherals. These horizontal networks spread memory bandwidth across the edge of the device, making it easier to saturate the memory bandwidth while avoiding routing congestion. Because the NoC is hard logic, it also reduces the need for soft interconnect logic, leaving more room for other IP functions.

The clock control segment contains a PLL for clock generation and a sub-system manager (SSM) for configuration. Other NoC segments interface with general purpose I/O (GPIO-B) banks where you can implement external memory interfaces. There are also segments to interface with the Universal Interface Bus (UIB) that connects to in-package high-bandwidth memory. The NoC segments contain switches, NoC initiators, and NoC targets. For details on each segment, refer to NoC Segments.

High-speed 512-bit links interconnect the switches within the NoC segments. There are separate sets of links carrying traffic left-to-right, and right-to-left, within the hard memory NoC. Each set of links has separate links for transaction requests and transaction responses.

NoC initiators connect AXI4 managers in the FPGA fabric to the hard memory NoC. NoC targets connect subordinate hardened memory controllers to the hard memory NoC.

You can choose to have the initiator return read data to M20K memory cells in a column adjacent to the NoC initiator using a configuration known as a fabric NoC. Because the data transfers directly into the FPGA fabric, this fabric NoC configuration reduces congestion at the edge of the device. Additionally, this configuration doubles the AXI4 read data width, enabling your design to fully utilize the high bandwidth memory and external memory interfaces while running at a lower operating frequency.

HBM2e memory connects to targets through the Universal Interface Bus (UIB). All access between the FPGA fabric and HBM2e memory is through the hard memory NoC. Refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide for details on the HBM2e memory.

You can implement external memory protocols, such as DDR5, in GPIO-B I/O blocks. You can also use GPIO-B blocks for implementing other I/O functions.

You have the option of accessing external memory interfaces using the hard memory NoC, or directly from the FPGA fabric bypassing the NoC, depending on memory speeds, protocols and your design needs. Refer to the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide for details on external memory protocols supported in GPIO-B blocks and when to use the hard memory NoC or bypass mode. Other I/O functions that you implement in GPIO-B blocks do not connect to the hard memory NoC and always bypass it directly in the FPGA fabric. Note that functions that bypass the hard memory NoC may prevent the use of certain NoC initiator locations. For more information refer to GPIO-B Bypass Mode and Initiators.

The hard memory NoC along the top edge of the die also connects to a multi-port front end (MPFE) for the Hard Processor System (HPS). The MPFE is located in the segment immediately next to the HPS and allows the HPS to initiate transactions on the hard memory NoC. The NoC initiators in the MPFE are similar to the NoC initiators that interface to the FPGA fabric, but do not have the option to use the fabric NoC configuration which transfers read data directly into M20K memory blocks. Refer to the Intel Agilex® 7 Hard Processor System Technical Reference Manual for details on the HPS.

Figure 2.  Intel Agilex® 7 M-Series Device Layout


Each hard memory NoC subsystem consists of several NoC segments connected horizontally by high-speed networks. Figure 2. Intel Agilex® 7 M-Series Device Layout shows the high-level layout of hard memory NoC elements in Intel Agilex® 7 M-Series devices. Along the top and bottom edge of the die are GPIO-B blocks for implementing external memory interfaces and UIB blocks for interfacing to HBM2e memory. Adjacent to these are the NoC GPIO-B and UIB segments that make up the hard memory NoC. NoC PLL and SSM segments are in the upper left and lower left corners. The vertical arrows extending from these segments into the die represent the optional fabric NoCs using M20K memory blocks.

Additionally, there is a service network within the hard memory NoC segments that runs in parallel to the main switch network. This service network connects the NoC SSM and the HPS AXI4 Lite initiator to AXI4 Lite targets. You can use this service network for sideband configuration and monitoring.

The following document sections describe the hard memory NoC segments and the fabric NoCs.

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