Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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5. Simulating NoC Designs

Behavioral, non-cycle accurate simulation of the NoC is available, in combination with your logic as either RTL or as a functional (non-timing) gate-level netlist. You can use these simulation methods to verify correct specification of the connectivity and addressing. However, you cannot model the throughput, latency, or traffic congestion on the hard memory NoC.

As with any other Intel FPGA IP, you can generate simulation models for NoC-related IP during IP HDL generation. Refer to Introduction to Intel FPGA IP Cores for instructions on incorporating these models into your simulation netlist and generating the appropriate simulation scripts.

The design netlist does not include NoC initiator-to-target connectivity and address- mapping, as Connecting NoC IP describes. To describe connectivity and address mapping for simulation, you must create initiator-to-target-connections by registration function calls that you include in simulation startup code. For example you can include the registration function calls in a Verilog initial block. Initiator simulation models provide the registration functions, and each call specifies the start address and address range of the connection to a specific target.

There are two distinct flows for generating a simulation include file that includes NoC connectivity, as NoC Design Flow Options describes:

  • Platform Designer Connection Flow—specify NoC connectivity and addressing within Platform Designer. When you generate HDL for your Platform Designer system, a simulation include file also generates with the NoC connectivity and addressing information.
  • NoC Assignment Editor Connection Flow—specify NoC connectivity and addressing in the NoC Assignment Editor. After saving your assignments and re-running Analysis & Elaboration, a simulation include file generates with the NoC connectivity and addressing information.

After generating the simulation include file using either connection flow, you must then add NoC connectivity and address mapping to your simulation netlist.