Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs 3. NoC Design Flow in Intel® Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Intel Agilex® 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

2.6.6. Horizontal Bandwidth Considerations

The horizontal network of switches that comprise the hard memory NoC connect with 512-bit wide links. Within each hard memory NoC, there are two 512-bit links carrying request transactions (AW, W, AR) left-to-right, and an additional two 512-bit links carrying request transactions right-to-left. Similarly, there are two 512-bit links carrying response transactions (R, B) left-to-right, and two 512-bit links carrying response transactions right-to-left.

You can calculate the maximum bandwidth of each bus by multiplying the NoC operating frequency with the width of the bus. For example, if the hard memory NoC is operating at 1.4 GHz, then each 64-byte bus contributes 89.6 GB/s. Table 4. Hard Memory NoC Horizontal Bandwidth summarizes the total bandwidth in each direction for each transaction type. Note that the Link Fmax and Max Bandwidth are lower on speed-grade 3 devices.

Table 4.  Hard Memory NoC Horizontal Bandwidth
Transaction Type Direction Link Count Link Width (bit) -1, -2 Speed Grade Link Fmax (GHz) -1, -2 Speed Grade Max Bandwidth (GB/s) -3 Speed Grade Link Fmax (GHz) -3 Speed Grade Max Bandwidth (GB/s)
Request (AW, W, AR) Left-to-Right 2 512 1.4 179.2 1.0 128
Right-to-Left 2 512 1.4 179.2 1.0 128

Response

(R, B)

Left-to-Right 2 512 1.4 179.2 1.0 128
Right-to-Left 2 512 1.4 179.2 1.0 128

Figure 13. Horizontal Link Allocation for Top-Edge NoC shows the links that connect to each NoC target. For each hard memory NoC along the top edge and bottom edge of the device, there are 24 NoC target interface bridges for connecting to HBM2e or external memory controllers. Again, for request transactions, there are two links in each direction. Each of these links connects to alternating NoC targets. LR0 and LR1 are the two links that carry traffic left-to-right. RL0 and RL1 are the two links that carry traffic right-to-left. Some of the connections are Local, which indicates that the initiator and target connect to the same switch. Traffic between such an initiator and target need not transfer horizontally.

Figure 13. Horizontal Link Allocation for Top-Edge NoC (AXI4-Lite Targets Not Shown)


Figure 14. Horizontal Link Allocation for Bottom-Edge NoC (AXI4-Lite Targets Not Shown)


When placing NoC initiators and NoC targets, placing some initiators to the left of their targets and some initiators to the right of their targets can reduce congestion on the hard memory NoC. Connections where the initiator is to the left of the target do not compete for bandwidth with connections where the initiator is to the right of the target because there are separate links for carrying traffic right-to-left versus left-to-right. Also, because separate links service consecutive targets (for example RL0 versus RL1 ), traffic to one target does not compete for bandwidth with traffic to an adjacent target.

For example, two initiators on the right side of the die with high bandwidth requirements for targets on the left side of the die can require communication over the same links if the RL0 link services both targets.

If the RL0 link services one of the targets, while the RL1 link services the other target, the two connections do not compete for bandwidth. Alternatively, if one of the initiators moves to the left of its target, the read traffic then uses one of the left-to-right links (for example LR0), and does not compete for bandwidth with other traffic using the right-to-left links (such as RL0).

Figure 15. Example NoC Exceeding Horizontal Bandwidth Limits shows an example of the top-edge hard memory NoC with targets in the UIB segment sending read data to initiators to the left side.

Figure 15. Example NoC Exceeding Horizontal Bandwidth Limits


In Figure 15. Example NoC Exceeding Horizontal Bandwidth Limits if each of these connections carries 20 GB/s of data, the maximum demand on the horizontal link is 120 GB/s. This maximum demand is greater than the 89.6 GB/s capacity of the link. Note that this example only shows targets that the LR0 horizontal link services. The LR1 link services other targets and does not compete for bandwidth with these initiator-target connections.

You can alleviate such bandwidth overload by placing some high bandwidth initiators to the left of their targets, and other high bandwidth initiators to the right of their targets.

Transactions between initiators and targets that connect directly to the same switch route locally, and need not transfer horizontally along these links. Therefore, the horizontal bandwidth that these local connections use does not count against the horizontal bandwidth limits.

In Figure 16. Example NoC Within Horizontal Bandwidth Limits, the locations of initiators from the previous example change. Some initiators are to the left of their targets (using the LR0 horizontal link), some initiators are to the right of their targets (using the RL0 horizontal link), and some initiators are directly across from their targets (represented by a vertical arrow using local connections instead of the horizontal links).

Figure 16. Example NoC Within Horizontal Bandwidth Limits


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