Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow

This topic describes how to connect the NoC IP and assign base addresses using the NoC Assignment Editor connection flow, as NoC Design Flow Options describes. When using the NoC Assignment Editor connection flow, you can configure and instantiate your NoC IP in either Platform Designer or in RTL.

Note: If you are using the Platform Designer connection flow, you can ignore this topic and refer instead to Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow.

To connect the NoC IP and assign base addresses using the NoC Assignment Editor connection flow, follow these steps:

  1. In Platform Designer System View tab, or in your design RTL, configure and instantiate all the NoC IP.
  2. If you instantiate your NoC IP in the System View tab, leave any AXI4 NoC manager, AXI4 NoC subordinate, HPS AXI4 NoC manager, and HPS AXI4 NoC subordinate interfaces on the NoC IP unconnected. If you are instantiating your NoC IP directly in RTL, these interfaces do not exist. In the System View tab, or in your design RTL, connect the NoC IP to external pins or FPGA core logic, as appropriate for your application.
    Note: If you are using Platform Designer, making these connections may require exporting signals as conduits when the connection targets are not part of the Platform Designer system.
  3. If you instantiate your NoC IP in the System View tab, save the system and click Generate HDL.
  4. Run Intel® Quartus® Prime Analysis & Elaboration on the design and then create NoC connections and base address assignments, as Creating NoC Assignments for Compilation describes.
    Note: The NoC Assignment Editor connection flow does not support RTL simulation until after you complete NoC connection and base address assignments in the NoC Assignment Editor.