Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
Document Table of Contents
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1.1. Introduction to Intel Agilex® 7 M-Series FPGAs

Intel Agilex® 7 M-Series FPGAs introduce an integrated Network-on-Chip (NoC) to facilitate high-bandwidth data movement between the FPGA core logic and memory resources, such as HBM2e and external memories, such as DDR5. The Intel Agilex® 7 M-Series FPGA implements the NoC as two independent hard memory NoCs running horizontally along the top edge and bottom edge of the die. These horizontal networks spread memory bandwidth across the edge of the device, making it easier to saturate the memory bandwidth while avoiding routing congestion. An additional feature known as the fabric NoC allows you to store read data from external memory directly in M20K memory blocks in the FPGA fabric, further reducing congestion along the die edge.

This document provides the following information about these NoC devices:

  • An introduction to NoC structures and typical applications.
  • Details on the NoC subsystem in Intel Agilex® 7 M-Series FPGAs.
  • How to create NoC designs in the Intel® Quartus® Prime Pro Edition software.
  • How to use NoC subsystem features to monitor performance during operation.
  • How to simulate designs using the NoC subsystem.
  • How to estimate power for designs using the NoC subsystem.