Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

1.3.1. General NoC Architecture

The NoC subsystem comprises a network of switches connected with high-speed data links. The NoC initiators and NoC targets connect into these switches. Initiators are bridges that interface with manager logic in your design that initiates read or write transactions.

Figure 1. General NoC Architecture Abstraction illustrates an example of a high-bandwidth, high-speed Network-on-Chip (NoC) interconnect architecture.

Figure 1. General NoC Architecture Abstraction


NoC targets are bridges that interface with subordinate IP that respond to these read or write transactions. Some subordinate IP, such as the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP, may connect to multiple targets. The NoC initiators and targets translate between the AXI4 and the internal NoC format.

In a typical transaction, an AXI manager posts transactions that the initiator block then converts into the internal format of the NoC. These transaction steps then reverse when the transaction translates back to AXI upon arrival at the subordinate memory IP. Multiple managers can issue read or write transactions simultaneously to different subordinates. The switch network routes each request independently, arbitrating between traffic, as necessary.

You can use the hardened NoC architecture to transport transactions to external memory. The hardened NoC infrastructure applies the advantages of large-scale networks to FPGAs. The NoC subsystem provides highly structured, flexible, and scalable on-chip memory access solutions for bandwidth demanding applications, such as real-time audio and video, network processing, high-performance computing, and other applications.