Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs 3. NoC Design Flow in Intel® Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Intel Agilex® 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

5.3. Contents of Simulation Registration Include File

The simulation registration include file generates into your project directory, in Verilog HDL format, with the name <top_module>_noc_sim.inc. This simulation registration include file has all the necessary registration information for each initiator-to-target connection using a SIM_TOP_PATH macro to specify the hierarchical path.

Note: This file is only available in Verilog HDL format. If your design uses VHDL, you must create a top-level wrapper in Verilog HDL to use this registration include file and perform a mixed-language simulation.

To use this file, edit your top-level simulation testbench to define the SIM_TOP_PATH macro to complete the hierarchical path to the initiators and targets relative to the testbench.

Once you define the SIM_TOP_PATH macro, use the `include directive to include this file into your simulation testbench and apply the registration statements. If your simulation environment instantiates these modules at multiple places in your hierarchy, redefine the SIM_TOP_PATH macro and re-include this file for each additional instantiation. Do not edit the simulation registration include file directly because the Compiler rewrites this file during each compilation.

The format for the registration statements in Verilog HDL is as follows. Use the Verilog HDL hierarchy delimiter, ., instead of the Intel® Quartus® Prime hierarchy delimiter, |. Also, express hexadecimal numbers using Verilog HDL format. 

<hierarchical initiator path name>.register_if\
   (<hierarchical target path name>.get_if(),\
   <hexadecimal base address>, \
     <hexadecimal span of memory>);

For example, the following registration statement specifies a connection with a base address of 0 and spanning 40000000 (hexadecimal) addresses: 

`SIM_TOP_PATH.noc_init|noc_init|iniu_0|initiator_inst_
0.register_if(`SIM_TOP_PATH.noc_hbm|noc_hbm|tniu_ch0_u0|target_0.target_inst_0.get_if(), 44'h0,
 44'h40000000);
Figure 55. Example Contents of Simulation Registration Include File Generation 


/*
File test_noc_sim.inc created by Quartus Version 23.3.0 Internal Build 81 08/20/2023 SC Pro Edition.
Description: This file contains simulation registration statements necessary to define connectivity 
and address mapping between initiators and targets in your hard memory NoC.
Instructions for Use: In your simulation testbench, define the SIM_TOP_PATH macro to complete the 
hierarchical path to the initiators and targets in the registration statements below. Once the 
SIM_TOP_PATH macro is defined, use a `include directive to include this file into your simulation 
testbench and apply the registration statements. If your simulation environment instantiates these 
modules at multiple places in your hierarchy, redefine the SIM_TOP_PATH macro and re-include this file 
for each additional instantiation.
This file will be overwritten upon rerun.
*/
initial begin
 #1;
 `SIM_TOP_PATH.noc_init|noc_init|iniu_0|initiator_inst_
0.register_if(`SIM_TOP_PATH.noc_hbm|noc_hbm|tniu_ch0_ch1_sb|target_0.target_lite_inst_0.get_if(),
44'h80000000, 44'h8000000);
 `SIM_TOP_PATH.noc_init|noc_init|iniu_0|initiator_inst_
0.register_if(`SIM_TOP_PATH.noc_hbm|noc_hbm|tniu_ch0_u0|target_0.target_inst_0.get_if(), 44'h0,
44'h40000000);
 `SIM_TOP_PATH.noc_init|noc_init|iniu_0|initiator_inst_
0.register_if(`SIM_TOP_PATH.noc_hbm|noc_hbm|tniu_ch0_u1|target_0.target_inst_0.get_if(),
44'h40000000, 44'h40000000);
 `SIM_TOP_PATH.noc_init|noc_init|iniu_1|initiator_inst_
0.register_if(`SIM_TOP_PATH.noc_hbm|noc_hbm|tniu_ch0_u0|target_0.target_inst_0.get_if(), 44'h0, 
44'h40000000);
`SIM_TOP_PATH.noc_init|noc_init|iniu_1|initiator_inst_
0.register_if(`SIM_TOP_PATH.noc_hbm|noc_hbm|tniu_ch0_u1|target_0.target_inst_0.get_if(),
44'h40000000, 44'h40000000);
end
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