Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
Document Table of Contents
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2.2.4. SDM Segment

The hard memory NoC on the bottom edge of the device also has a segment that spans the Secure Device Manager (SDM). There is no connection between the SDM and the hard memory NoC, and all signals from the SDM bypass the hard memory NoC. This NoC segment spans one clock sector and consists of the following:

  • One AXI4 initiator on the FPGA fabric side.
  • A switch that transfers packets laterally along the hard memory NoC and connects to the AXI4 initiator.
Figure 6. NoC SDM Segment


Note: There is an additional service network running parallel to the main switch network. This service network connects the NoC SSM to the AXI4 Lite initiators and targets. NoC initiators can send transactions over the main network to the NoC SSM to access the service network for sideband configuration and system monitoring. Figure 6. NoC SDM Segment does not show this network.