Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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3.3.1. NoC Initiators for Hard Processor Systems

Configure NoC initiators for hard processor systems (HPS) using the Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP in Platform Designer. To enable NoC initiators for HPS when parameterizing the Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP, follow these steps:

  1. Click the SDRAM tab in the IP Parameter Editor.
  2. Turn on the Enable HPS-to-HNOC-INIU AXI Interfaces option.
  3. Select one of the following HNOC Interface Configuration options:
    • Single-Channel—this configuration instantiates one initiator in the MPFE. Select Single-Channel configuration for memory capacity up to 64 GB when you do not require interleaving.
    • Dual-Channel—this configuration instantiates two initiators in the MPFE. You can also turn on the Enable Interleave Mode option to enable logic in the MPFE to interleave between the HPS-EMIF channels. Select Dual-Channel configuration for memory capacity above 64 GB or when enabling interleaving.
Figure 19. SDRAM Tab of Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP Parameter Editor


NoC initiators for HPS can only connect to NoC targets in External Memory Interfaces for HPS Intel FPGA IP. For further information on HPS, refer to the Intel Agilex 7 Hard Processor System Component Reference Manual.