Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Public
Document Table of Contents
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2.6.2. Determining the Number of NoC Initiators

The number of NoC initiators in your design depends on the memory bandwidth requirements of the user logic functions. Calculate the bandwidth that an individual NoC initiator can support by multiplying the width of its data bus by the clock frequency of the logic driving the NoC initiator. Higher operating frequencies may require fewer NoC initiators but can encounter more difficulty when closing timing. Using the 512/576b fabric NoC option reduces shoreline congestion and allows timing closure at faster clock rates.

The NoC subsystems along the top and bottom edges of the FPGA die are independent. Therefore, plan the number of NoC initiators for each subsystem separately, based on the memory resources that you use along each die edge.

Note: You can configure the NoC Initiator Intel FPGA IP to share a NoC initiator bridge between an AXI4 interface and up to four AXI4-Lite interfaces, unless you are using the fabric NoC on the same bridge.