Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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3.3. NoC Building Blocks

Creating a hard memory NoC design involves the following building blocks that you configure using corresponding Intel FPGA IP:

  • NoC Initiators—for fabric-facing initiators, configure using the NoC Initiator Intel FPGA IP. If you are using the Hard Processor System Intel Agilex 7 /Agilex 9 FPGA IP, this IP includes the HPS-facing initiators.
  • NoC Targets—for memory resources that the FPGA fabric uses, you configure the targets using the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP and External Memory Interfaces (EMIF). For memory resources that the HPS uses, you configure the targets using the External Memory Interfaces for HPS Intel FPGA IP.
  • NoC Clock Control—configure the NoC PLL and NoC SSM using the NoC Clock Control Intel FPGA IP.