7.1.2. NoC Initiator Intel FPGA IP Interfaces
This section describes the interfaces on the NoC Initiator Intel FPGA IP for the AXI4 or AXI4 Lite interfaces to AXI4 managers in your logic. Connections between the NoC Initiator Intel FPGA IP and the hard memory NoC are not modeled in RTL. Rather, you specify these connections by making assignments in the NoC Assignment Editor. For more information about making these assignments, refer to Making NoC Assignments.