Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
Document Table of Contents
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2.2.5. PLL and SSM Segment

The end NoC segment for each hard memory NoC contains the NoC PLL and the NoC subsystem manager (SSM). The NoC PLL generates the clocking for the hard memory NoC. The NoC SSM connects to a service network to configure the hard memory NoC and to read status registers for observability and debug purposes. The NoC SSM uses a non-user accessible AXI4 Lite initiator to connect to the service network.

Figure 7. NoC PLL and SSM Segment

Note: Figure 7. NoC PLL and SSM Segment does not show the reference clock for the PLL nor the clocks generated by the PLL.

The NoC SSM segment provides a transparent bridge between the hard memory NoC and service network. This bridge enables fabric AXI4 initiators to access AXI4 Lite targets.