Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers

The High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP and the External Memory Interfaces (EMIF) IP each contain the Hard memory NoC targets. These IP have separate AXI4 and AXI4 Lite targets. Interface Planner displays both types of targets as AXI4 NoC subordinate interfaces.

For High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 FPGA IP, the AXI4 targets have interface names, such as t_ch<number>_u<number>_axinoc. The AXI4 Lite targets have interface names, such as t_ch<number>_ch<number>_sb_axinoc.

For External Memory Interface (EMIF) IP, the AXI4 targets have interface names, such as t<number>_axi4noc. The AXI4 Lite targets have interface names, such as t<number>_axilnoc. The AXI4 NoC subordinate interfaces do not exist in the RTL representation of these IP.

The following table shows the various interface name formats. Make any clocking, reset, calibration, or external I/O connections for these IP in accordance with the IP user guide guidelines for these IP.

Table 6.  Interface Name Formats
Interface Type Interface Name Format
HBM2E Interface AXI4 targets t_ch<number>_u<number>_axinoc
HBM2E Interface AXI4-Lite targets t_ch<number>_ch<number>_sb_axinoc
EMIF IP AXI4 targets t<number>_axi4noc
EMIF IP AXI4-Lite targets t<number>_axilnoc
  • If you are using the Platform Designer connection flow, as NoC Design Flow Options describes, instantiate your NoC IP in Platform Designer and connect each AXI4 NoC subordinate interface to one or more AXI4 NoC manager interfaces in the System View tab. Only connect AXI4 NoC subordinate interfaces on memory resources for fabric AXI4 managers to NoC Initiator Intel FPGA IP. Do not connect memory resources for fabric AXI4 managers to HPS initiators in the Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP. After connecting AXI4 NoC manager and AXI4 NoC subordinate interfaces, click the Address Map tab to specify the base address for each connection. If an AXI4 NoC manager interface connects to multiple AXI4 NoC subordinate interfaces, ensure each connection has a unique starting address. You can click the Assign Base Addresses button to allow Platform Designer to assign addresses automatically.
  • If you are using the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, and using Platform Designer to instantiate your NoC IP, do not connect the AXI4 NoC subordinate interfaces in the Platform Designer System View tab. After running Intel® Quartus® Prime Analysis & Elaboration, you use the NoC Assignment Editor to define connectivity and addressing to prepare your design for RTL simulation.
  • If you are using the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, and instantiating your NoC IP directly in RTL, the AXI4 NoC subordinate interfaces do not exist. After running Intel® Quartus® Prime Analysis & Elaboration, you use the NoC Assignment Editor to define connectivity and addressing to prepare your design for RTL simulation.

Refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 FPGA IP User Guide for information on the High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 FPGA IP. Refer to the External Memory Interfaces Intel Agilex 7 M-Series FPGA IP User Guide for information on the External Memory Interfaces (EMIF) IP