Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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Document Table of Contents
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7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals

In the Platform Designer view of the NoC Initiator Intel FPGA IP, there are additional AXI4 NoC manager port(s), one for each AXI4 or AXI4 Lite interface. If you are using the early RTL simulation flow, you can connect this port to an AXI4 NoC subordinate port to specify an initiator-to-target connection in the Platform Designer System View tab.

Platform Designer uses this initiator-to-target connection when generating the simulation registration include file. You can locate AXI4 NoC subordinate ports in IP containing NoC targets, such as the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP, or the External Memory Interfaces (EMIF) IP. For more information on the early RTL simulation flow, refer to Simulating NoC Designs. If you are not using the early RTL simulation flow, you can leave the AXI4 NoC manager ports unconnected in Platform Designer. Regardless of whether you connect the AXI4 NoC manager ports in Platform Designer, the generated HDL for your system does not show the AXI4 NoC manager port on the NoC Initiator Intel FPGA IP.

If you are designing your NoC system in RTL, the NoC Initiator Intel FPGA IP does not have an AXI4 NoC manager port.