Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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7. Hard Memory NoC IP Reference

This chapter provides interface, signal, and parameter information for the NoC Initiator Intel FPGA IP and the NoC Clock Control Intel FPGA IP. The targets for the hard memory NoC in Intel Agilex® 7 M-Series FPGAs are part of the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP or the External Memory Interfaces (EMIF) IP.

For information on NoC targets in the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP, refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide.

For information on NoC targets in external memory interfaces, refer to the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide.