Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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2.6.7. GPIO-B Bypass Mode and Initiators

Another consideration for hard memory NoC target and initiator placement is the use of GPIO-B blocks to implement low-speed memory configurations or GPIO functions. This technique bypasses the hard memory NoC. Due to device routing limitations, you cannot simultaneously use GPIO-B blocks implementing functions in bypass mode, and all of the NoC initiators directly opposite these GPIO-B blocks. Thus, using GPIO-B blocks in bypass mode prevents placement of NoC initiators in certain locations. Conversely, initiator placement can prevent certain GPIO-B blocks from implementing functions using bypass mode.

Figure 17. Routing Choice: NoC Initiator Usage Versus NoC Bypass Usage


Use the Interface Planner in the Intel® Quartus® Prime Pro Edition software to obtain an accurate view of the placement restrictions. Place GPIO-B functions that bypass the hard memory NoC first, preferably using a GPIO-B at an extreme end of one of the hard memory NoCs. Use Interface Planner to generate legal locations for placement of initiators. Interface Planner displays the NoC initiator locations that are available and the locations that are unavailable.

For additional details on using the Interface Planner tool to plan periphery functions in Intel Agilex® 7 M-Series FPGAs, refer to Making Physical Assignments Using Interface Planner.

For general information on using the Interface Planner tool, refer to Intel® Quartus® Prime Pro Edition User Guide: Design Constraints.