Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 12/04/2023
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3.2. Using NoC Example Designs

To quickly start a design from a complete, pre-verified design example that uses the hard memory NoC, you can access a design example from within the Intel® Quartus® Prime Pro Edition software. These design examples include the following:

  • A complete Intel® Quartus® Prime project that contains a Platform Designer system that instantiates and connects the hard memory NoC IP, including the following IP:
    • NoC Initiator Intel FPGA IP connected to traffic generators.
    • Targets within the memory IP (HBM2e Intel FPGA IP or External Memory Controller (EMIF) IP).
    • Clock Control Intel FPGA IP.
  • Assignments to implement grouping, connectivity, and address mapping for the use case.
  • Assignment for default read and write bandwidth requirements based on optimal configuration and initiator bridge placement. You can change these settings independently for each initiator-target connection in the NoC Assignment Editor.
  • Simulation models and testbench.

The following steps summarize the process to create a hard memory NoC user design based on an available design example in the Intel® Quartus® Prime Pro Edition software. These example designs specify NoC connectivity and addressing using the NoC Assignment Editor. Because these example design simulation testbenches include the necessary registration statements, you can perform RTL simulation before running Analysis & Elaboration.

  1. In the Intel® Quartus® Prime software IP Catalog or Platform Designer IP Catalog, double-click the appropriate memory IP:
    • High Bandwidth Memory (HBM2e) Interface Intel Agilex® 7 FPGA IP

      Or

    • External Memory Interfaces (EMIF) IP
  2. In the IP parameter editor, configure the desired parameters for your use case on the General tab. On the Example Design tab, configure the options related to your hard memory NoC implementation.
  3. Click the Generate Example Design button. Specify a location and file name to generate and open the example design.

For details on characteristics and accessing HBM2e and eternal memory Intel FPGA IP example designs, refer to the following resources.